AD9520-1SLASHPCBZ datasheet(65/80 Pages) AD

65 / 80 page

Data Sheet

AD9520-1

Rev. B | Page 65 of 80

Table 54. PLL

Reg.

Addr.

(Hex)

Bits

Name

Description

0x010 7

PFD polarity

Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip VCO requires

positive polarity; Bit 7 = 0b.

0: positive (higher control voltage produces higher frequency) (default).

1: negative (higher control voltage produces lower frequency).

[6:4]

CP current

Charge pump current (with CPRSET = 5.1 kΩ).

Bit

ICP (mA)

0.6

1.2

1.8

2.4

3.0

3.6

4.2

4.8 (default)

[3:2]

CP mode

Charge pump operating mode.

Bit

Charge Pump Mode

High impedance state.

Forces source current (pump up).

Forces sink current (pump down).

Normal operation (default).

[1:0]

PLL power-down PLL operating mode.

Bit

Mode

Normal operation; this mode must be selected to use the PLL.

Asynchronous power-down (default).

Unused.

Synchronous power-down.

0x011 [7:0]

14-bit R counter,

Bits[7:0] (LSB)

Reference divider LSBs—lower eight bits. The reference divider (also called the R divider or R counter) is 14 bits long.

The lower eight bits are in this register (default: 0x01).

0x012 [7:6]

Unused

Unused.

[5:0]

14-bit R counter,

Bits[13:8] (MSB)

Reference divider MSBs—upper six bits. The reference divider (also called the R divider or R counter) is 14 bits long.

The upper six bits are in this register (default: 0x00).

0x013 [7:6]

Unused

Unused.

[5:0]

6-bit A counter

A counter (part of N divider). The N divider is also called the feedback divider (default: 0x00).

0x014 [7:0]

13-bit B counter,

Bits[7:0] (LSB)

B counter (part of N divider)—lower eight bits. The N divider is also called the feedback divider (default: 0x03).

0x015 [7:5]

Unused

Unused.

[4:0]

13-bit B counter,

Bits[12:8] (MSB)

B counter (part of N divider)—upper five bits. The N divider is also called the feedback divider (default: 0x00).

0x016 7

Set CP pin

to VCP/2

Sets the CP pin to one-half of the VCP supply voltage.

0: CP normal operation (default).

1: CP pin set to VCP/2.

Reset R counter

Resets R counter (R divider).

0: normal (default).

1: holds R counter in reset.

Reset A and B

counters

Resets A and B counters (part of N divider).

0: normal (default).

1: holds A and B counters in reset

Reset all

counters

Resets R, A, and B counters.

0: normal (default).

1: holds R, A, and B counters in reset.

B counter bypass B counter bypass. This is valid only when operating the prescaler in FD mode.

0: normal (default).

1: B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider.

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