AD9520-1SLASHPCBZ datasheet(35/80 Pages) AD

35 / 80 page

Data Sheet

AD9520-1

Rev. B | Page 35 of 80

On-Chip VCO

The AD9520-1 includes an on-chip VCO covering the frequency

range shown in Table 2. The calibration procedure ensures that

the VCO operating voltage is centered for the desired VCO

frequency. The VCO must be calibrated when the VCO loop

is first set up, as well as any time the nominal VCO frequency

changes. However, once the VCO is calibrated, the VCO has

sufficient operating range to stay locked over temperature and

voltage extremes without needing additional calibration. See the

VCO Calibration section for additional information.

The on-chip VCO is powered by an on-chip, low dropout (LDO),

linear voltage regulator. The LDO provides some isolation of

the VCO from variations in the power supply voltage level. The

BYPASS pin should be connected to ground by a 220 nF capacitor

to ensure stability. This LDO employs the same technology that

is used in the anyCAP® line of regulators from Analog Devices, Inc.,

making it insensitive to the type of capacitor used. Driving an

external load from the BYPASS pin is not supported.

PLL External Loop Filter

When using the internal VCO, reference the external loop filter

to the BYPASS pin for optimal noise and spurious performance.

Figure 39 shows an example of an external loop filter for the PLL.

This third-order design usually offers the best performance. A loop

filter must be calculated for each desired PLL configuration. The

component values depend upon the VCO frequency, the KVCO, the

PFD frequency, the CP current, the desired loop bandwidth, and

the desired phase margin. The loop filter affects the phase noise,

loop settling time, and loop stability. A knowledge of PLL theory

is necessary for understanding loop filter design. Available tools,

such as ADIsimCLK, can help with the calculation of a loop

filter according to the application requirements.

VCO

CHARGE

PUMP

BYPASS

31pF

CBP = 220nF

AD9520

Figure 39. Example of External Loop Filter for a PLL Using the Internal VCO

When using an external VCO, ensure that the external loop

filter is referenced to ground. See Figure 40 for an example of an

external loop filter for a PLL using an external VCO.

CLK/CLK

EXTERNAL

VCO/VCXO

CHARGE

PUMP

AD9520

Figure 40. Example of External Loop Filter for a PLL Using an External VCO

Figure 41 and Figure 42 show the typical PLL loop filters that

are used to generate the plots in Figure 30 and Figure 32,

respectively.

62pF

33pF

240nF

C12

220nF

BYPASS

CAPACITOR

FOR LDO

820Ω

390Ω

BYPASS

Figure 41. Typical PLL Loop Filter Used for Clock Generation

1.5nF

2.2nF

4.7µF

C12

220nF

BYPASS

CAPACITOR

FOR LDO

2.1kΩ

3kΩ

BYPASS

Figure 42. Typical PLL Loop Filter Used for Clock Cleanup

PLL Reference Inputs

The AD9520-1 features a flexible PLL reference input circuit

that allows a fully differential input, two separate single-ended

inputs, or a 16.67 MHz to 33.33 MHz crystal oscillator with an

on-chip maintaining amplifier. An optional reference clock

doubler can be used to double the PLL reference frequency. The

input frequency range for the reference inputs is specified in

Table 2. Both the differential and the single-ended inputs are

self-biased, allowing for easy ac coupling of input signals.

Either a differential or a single-ended reference must be specifically

enabled. All PLL reference inputs are off by default.

The differential input and the single-ended inputs share two pins,

REFIN and REFIN (REF1 and REF2, respectively). The desired

reference input type is selected and controlled by Register 0x01C

(see Table 50 and Table 54).

When the differential reference input is selected, the self-bias

level of the two sides is offset slightly (~100 mV, see Table 2) to

prevent chattering of the input buffer when the reference is slow

or missing. This increases the voltage swing that is required of

the driver and overcomes the offset. The differential reference

input can be driven by either ac-coupled LVDS or ac-coupled

LVPECL signals.

The single-ended inputs can be driven by either a dc-coupled

CMOS level signal or an ac-coupled sine wave or square wave.

To avoid input buffer chatter when a single-ended, ac-coupled

input signal stops toggling, the user can set Register 0x018[7]

to 1b. This shifts the dc offset bias point down 140 mV. To increase

isolation and reduce power, each single-ended input can be

independently powered down.

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