AD9520-1SLASHPCBZ datasheet(28/80 Pages) AD

28 / 80 page

AD9520-1

Data Sheet

Rev. B | Page 28 of 80

THEORY OF OPERATION

OPERATIONAL CONFIGURATIONS

The AD9520-1 can be configured in several ways. These

configurations must be set up by loading the control registers

(see Table 50 to Table 61). Each section or function must be

individually programmed by setting the appropriate bits in the

corresponding control register or registers. After the desired

configuration is programmed, the user can store these values

in the on-board EEPROM to allow the part to power up in the

desired configuration without user intervention.

Mode 0—Internal VCO and Clock Distribution

When the internal VCO and PLL are used, the VCO divider

must also be used, in most cases, to ensure that the frequency

presented to the channel dividers does not exceed its specified

maximum frequency (see Table 3). The exceptions to this are

the VCO direct mode and cases where the VCO frequency is

≤1600 MHz. The internal PLL uses an external loop filter to set

the loop bandwidth. The external loop filter is also crucial to

the loop stability.

When the internal VCO is used, the VCO must be calibrated

(Register 0x018[0] = 1b) to ensure optimal performance.

For internal VCO and clock distribution applications, use the

Table 22. Settings When Using Internal VCO

Description

0x010[1:0] = 00b

PLL normal operation (PLL on)

0x010 to 0x01E

PLL settings; select and enable a reference

input; set R, N (P, A, B), PFD polarity, and ICP

according to the intended loop configuration

0x1E1[1] = 1b

Select VCO as the source

0x01C[2:0]

Enable reference inputs

0x1E0[2:0]

Set VCO divider

0x1E1[0] = 0b

Use the VCO divider as the source for the

distribution section

0x018[0] = 0b,

0x232[0] = 1b

Clear previous VCO calibration and issue

IO_UPDATE (not necessary the first time after

power-up, but must be done subsequently)

0x018[0] = 1b,

0x232[0] = 1b

Initiate VCO calibration, issue IO_UPDATE

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