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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9520-1/PCBZ датащи(PDF) 4 Page - Analog Devices |
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AD9520-1/PCBZ датащи(HTML) 4 Page - Analog Devices |
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4 / 80 page  AD9520-1 Data Sheet Rev. B | Page 4 of 80 SPECIFICATIONS Typical is given for VS = VS_DRV = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted. Minimum and maximum values are given over full VS and TA (−40°C to +85°C) variation. POWER SUPPLY REQUIREMENTS Table 1. Parameter Min Typ Max Unit Test Conditions/Comments POWER PINS VS 3.135 3.3 3.465 V 3.3 V ± 5% VS_DRV 2.375 VS V Nominally 2.5 V to 3.3 V ± 5% VCP VS 5.25 V Nominally 3.3 V to 5.0 V ± 5% CURRENT SET RESISTORS RSET Pin Resistor 4.12 kΩ Sets internal biasing currents; connect to ground CPRSET Pin Resistor 5.1 kΩ Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 µA); actual current can be calculated by CP_lsb = 3.06/CPRSET; connect to ground BYPASS PIN CAPACITOR 220 nF Bypass for internal LDO regulator; necessary for LDO stability; connect to ground PLL CHARACTERISTICS Table 2. Parameter Min Typ Max Unit Test Conditions/Comments VCO (ON CHIP) Frequency Range 2270 2650 MHz VCO Gain (KVCO) 50 MHz/V See Figure 8 Tuning Voltage (VT) 0.5 VCP − 0.5 V VT ≤ VS when using internal VCO Frequency Pushing (Open-Loop) 1 MHz/V Phase Noise at 1 kHz Offset −50 dBc/Hz f = 2475 MHz Phase Noise at 100 kHz Offset −107 dBc/Hz f = 2475 MHz Phase Noise at 1 MHz Offset −126 dBc/Hz f = 2475 MHz REFERENCE INPUTS Differential Mode (REFIN, REFIN) Differential mode (can accommodate single-ended input by ac grounding undriven input) Input Frequency 0 250 MHz Frequencies below about 1 MHz should be dc- coupled; be careful to match VCM (self-bias voltage) Input Sensitivity 280 mV p-p PLL figure of merit (FOM) increases with increasing slew rate (see Figure 12); the input sensitivity is sufficient for ac-coupled LVDS and LVPECL signals Self-Bias Voltage, REFIN 1.35 1.60 1.75 V Self-bias voltage of REFIN1 Self-Bias Voltage, REFIN 1.30 1.50 1.60 V Self-bias voltage of REFIN1 Input Resistance, REFIN 4.0 4.8 5.9 kΩ Self-biased1 Input Resistance, REFIN 4.4 5.3 6.4 kΩ Self-biased1 Dual Single-Ended Mode (REF1, REF2) Two single-ended CMOS-compatible inputs Input Frequency (AC-Coupled with DC Offset Off) 10 250 MHz Slew rate must be >50 V/µs Input Frequency (AC-Coupled with DC Offset On) 250 MHz Slew rate must be >50 V/µs, and input amplitude sensitivity specification must be met; see the input sensitivity parameter Input Frequency (DC-Coupled) 0 250 MHz Slew rate > 50 V/µs; CMOS levels Input Sensitivity (AC-Coupled with DC Offset Off) 0.55 3.28 V p-p VIH should not exceed VS Input Sensitivity (AC-Coupled with DC Offset On) 1.5 2.78 V p-p VIH should not exceed VS Input Logic High, DC Offset Off 2.0 V Input Logic Low, DC Offset Off 0.8 V Input Current −100 +100 µA Input Capacitance 2 pF Each pin, REFIN (REF1)/REFIN (REF2) |
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