AD9520-1SLASHPCBZ datasheet(44/80 Pages) AD

44 / 80 page

AD9520-1

Data Sheet

Rev. B | Page 44 of 80

In addition, the channel dividers allow a coarse phase offset or

delay to be set. Depending on the division selected, the output

can be delayed by up to 15 input clock cycles. For example, if

the frequency at the input of the channel divider is 1 GHz, the

channel divider output can be delayed by up to 15 ns. The

divider outputs can also be set to start high or to start low.

Operation Modes

There are three clock distribution operating modes, and these

are shown in Figure 50. One of these modes uses the internal

VCO, whereas the other two modes bypass the internal VCO

and use the signal provided on the CLK/CLK pins.

In Mode 0 (internal VCO mode), there are two signal paths

available. In the first path, the VCO signal is sent to the VCO

divider and then to the individual channel dividers. In the

second path, the user bypasses the VCO and channel dividers

and sends the VCO signal directly to the drivers.

When CLK is selected as the source, it is not necessary to use the

VCO divider if the CLK frequency is less than the maximum

channel divider input frequency (1600 MHz); otherwise, the

VCO divider must be used to reduce the frequency going to

the channel dividers.

Table 32 shows how the VCO, CLK, and VCO divider are selected.

determines whether the VCO divider is used. It is not possible

to select the VCO without using the VCO divider.

Table 32. Operation Modes

Mode

Channel Divider Source

VCO Divider

Bit 1

Bit 0

CLK

Used

CLK

Not used

VCO

Used

Not allowed

CLK or VCO Direct-to-LVPECL Outputs

It is possible to connect either the internal VCO or the CLK

(whichever is selected as the input to the VCO divider) directly

to the LVPECL outputs. This configuration can pass frequencies

up to the maximum frequency of the VCO directly to the LVPECL

outputs. However, the LVPECL outputs may not be able to meet

the VOD specification in Table 4 at the highest frequencies.

Either the internal VCO or the CLK can be selected as the

source for the direct-to-output signal routing. To connect the

LVPECL outputs directly to the internal VCO or CLK, the VCO

divider must be selected as the source to the distribution

section, even if no channel uses it.

Table 33. Routing VCO Divider Input Directly to the Outputs

Selection

0x1E1[1:0] = 00b

CLK is the source; VCO divider selected

0x1E1[1:0] = 10b

VCO is the source; VCO divider selected

0x192[1] = 1b

Direct-to-output OUT0, OUT1, OUT2

0x195[1] = 1b

Direct-to-output OUT3, OUT4, OUT5

0x198[1] = 1b

Direct-to-output OUT6, OUT7, OUT8

0x19B[1] = 1b

Direct-to-output OUT9, OUT10, OUT11

Clock Frequency Division

The total frequency division is a combination of the VCO

divider (when used) and the channel divider. When the VCO

divider is used, the total division from the VCO or CLK to the

output is the product of the VCO divider (1, 2, 3, 4, 5, and 6)

and the division of the channel divider. Table 34 shows how the

frequency division for a channel is set.

Table 34. Frequency Division

CLK or VCO

Selected

VCO

Divider

Setting1

Channel

Divider

Setting

Direct-to-

Output

Setting

Resulting

Frequency

Division

CLK or VCO

input

1 to 6

Don’t

care

Enable

CLK or VCO

input

1 to 6

2 to 32

Disable

(1 to 6) ×

(2 to 32)

CLK or VCO

input

2 to 6

Bypass

Disable

(2 to 6) × (1)

CLK or VCO

input

Bypass

Disable

Output static

(illegal state)

CLK (internal

VCO off)

VCO

divider

bypassed

Bypass

Don’t care

CLK (internal

VCO off)

VCO

divider

bypassed

2 to 32

Don’t care

2 to 32

The bypass VCO divider (Register 0x1E1[0] = 1b) is not the same as VCO

divider = 1 (divide-by-1).

MODE 0 (INTERNAL VCO MODE)

CLK

DIVIDE BY 1,

2, 3, 4, 5, OR 6

CLOCK

DISTRI-

BUTION

PLL

DISTRIBUTION

CLOCK

MODE 1 (CLOCK DISTRIBUTION MODE)

DISTRIBUTION

CLOCK

MODE 2 (HF CLOCK DISTRIBUTION MODE)

CLK

DIVIDE BY 1,

2, 3, 4, 5, OR 6

CLOCK

DISTRI-

BUTION

PLL

CLK

DIVIDE BY 1,

2, 3, 4, 5, OR 6

CLOCK

DISTRI-

BUTION

PLL

DISTRIBUTION

CLOCK

Figure 50. Simplified Diagram of the Three Clock Distribution Operation Modes

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