AD9520-1SLASHPCBZ datasheet(41/80 Pages) AD

41 / 80 page

Data Sheet

AD9520-1

Rev. B | Page 41 of 80

PROGRAMMABLE

N DELAY

CLK

REF1

REF2

BUF

STATUS

VCO STATUS

REFERENCE

SWITCHOVER

REF_SEL

CPRSET VCP

GND

RSET

DISTRIBUTION

REFERENCE

REFMON

STATUS

P, P + 1

PRESCALER

A/B

COUNTERS

N DIVIDER

BYPASS

LOW DROPOUT

REGULATOR (LDO)

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

CHARGE

PUMP

HOLD

DIVIDE BY 1,

2, 3, 4, 5, OR 6

ZERO DELAY BLOCK

FROM CHANNEL

DIVIDER 0

VS_DRV

REFIN

OPTIONAL

REFIN

Figure 48. Reference and VCO/CLK Frequency Status Monitors

Frequency Status Monitors

The AD9520-1 contains three frequency status monitors that

are used to indicate if the PLL reference (or references, in the case

of single-ended mode) and the VCO/CLK input have fallen

below a threshold frequency. Note that the VCO frequency

monitor becomes a CLK input frequency monitor if the CLK

input is selected instead of the internal VCO. Figure 48 shows

the location of the frequency status monitors in the PLL.

The PLL reference monitors have two threshold frequencies:

normal and extended (see Table 17). The reference frequency

monitor thresholds are set in Register 0x01A[6].

VCO Calibration

The AD9520-1 on-chip VCO must be calibrated to ensure

proper operation over process and temperature. The VCO

calibration is controlled by a calibration controller running off a

divided REFIN clock. The calibration requires that the PLL be

set up properly to lock the PLL loop and that the REFIN clock

be present. The REFIN clock must come from a stable source

external to the AD9520-1.

VCO calibration can be performed two ways: automatically at

power-up and manually. Automatic VCO calibration occurs when

the EEPROM is set to automatically load the preprogrammed

values in the EEPROM and then automatically calibrate the VCO.

For the automatic calibration to complete, a valid reference must

be provided at power-up. If no valid reference is provided, the

user must calibrate the VCO manually.

During the first initialization after a power-up or a reset of

the AD9520-1, a manual VCO calibration sequence is initiated

by setting Register 0x018[0] = 1b. This can be done as part of

the initial setup before executing an update all registers operation

(IO_UPDATE, Register 0x232[0] = 1b).

Subsequent to the initial setup, a VCO calibration sequence

is initiated by resetting Register 0x018[0] = 0b, executing an

IO_UPDATE, setting Register 0x018[0] = 1b, and executing

another IO_UPDATE. A readback bit (Register 0x01F[6])

indicates when VCO calibration is finished by returning a logic

true (that is, 1b).

The sequence of operations for the VCO calibration follows:

Program the PLL registers to the proper values for the PLL

loop. Note that the VCO divider (Register 0x1E0[2:0])

must not be set to static during VCO calibration.

Ensure that the input reference signal is present.

For initial setting of the registers after a power-up or reset,

initiate a VCO calibration by setting Register 0x018[0] = 1b.

Subsequently, whenever a calibration is desired, set

A SYNC operation is initiated internally, causing the outputs

to go to a static state determined by normal SYNC function

operation.

VCO is calibrated to the desired setting for the requested

VCO frequency.

Internally, the SYNC signal is released, allowing outputs to

continue clocking.

The PLL loop is closed.

The PLL locks.

A SYNC is executed during the VCO calibration; therefore, the

outputs of the AD9520-1 are held static during the calibration,

which prevents unwanted frequencies from being produced.

However, at the end of a VCO calibration, the outputs may

resume clocking before the PLL loop is completely settled.

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