AD9520-1SLASHPCBZ datasheet(38/80 Pages) AD

38 / 80 page

AD9520-1

Data Sheet

Rev. B | Page 38 of 80

Digital Lock Detect (DLD)

By selecting the proper output through the mux on each pin, the

DLD function is available at the LD, STATUS, and REFMON pins.

The digital lock detect circuit indicates a lock when the time

difference of the rising edges at the PFD inputs is less than a

specified value (the lock threshold). The loss of a lock is indicated

when the time difference exceeds a specified value (the unlock

threshold). Note that the unlock threshold is wider than the

lock threshold, which allows some phase error in excess of the

lock window to occur without chattering on the lock indicator.

The lock detect window timing depends on the value of the

CPRSET resistor, as well as three settings: the digital lock

detect window bit (Register 0x018[4]), the antibacklash pulse

width bit (Register 0x017[1:0], see Table 2), and the lock detect

counter (Register 0x018[6:5]). The lock and unlock detection

values listed in Table 2 are for the nominal value of CPRSET =

5.11 kΩ. Doubling the CPRSET value to 10 kΩ doubles the

values in Table 2.

A lock is not indicated until there is a programmable number of

consecutive PFD cycles with a time difference that is less than the

lock detect threshold. The lock detect circuit continues to indicate

a lock until a time difference that is greater than the unlock

threshold occurs on a single subsequent cycle. For the lock detect

to work properly, the period of the PFD frequency must be

greater than the unlock threshold. The number of consecutive PFD

cycles required for lock is programmable (Register 0x018[6:5]).

Note that, in certain low (<500 Hz) loop bandwidth, high phase

margin cases, the DLD may chatter during acquisition, which

can cause the AD9520-1 to automatically enter and exit

holdover. To avoid this problem, it is recommended that the

user provide for a capacitor to ground on the LD pin such that

current source digital lock detect (CSDLD) mode can be used.

Analog Lock Detect (ALD)

The AD9520-1 provides an ALD function that can be selected

for use at the LD pin. There are two operating modes for ALD:

•

N-channel open-drain lock detect. This signal requires a

pull-up resistor to the positive supply, VS. The output is

normally high with short, low going pulses. Lock is

indicated by the minimum duty cycle of the low going pulses.

•

P-channel open-drain lock detect. This signal requires a

pull-down resistor to GND. The output is normally low with

short, high going pulses. Lock is indicated by the minimum

duty cycle of the high going pulses.

AD9520

ALD

VOUT

VS = 3.3V

Figure 44. Example of Analog Lock Detect Filter Using

N-Channel Open-Drain Driver

The analog lock detect function requires an RC filter to provide a

logic level indicating lock/unlock. The ADIsimCLK tool can be

used to help the user select the right passive component values

for ALD to ensure its correct operation.

Current Source Digital Lock Detect (CSDLD)

During the PLL locking sequence, it is normal for the DLD

signal to toggle a number of times before remaining steady

when the PLL is completely locked and stable. There may be

applications where it is desirable to have DLD asserted only

after the PLL is solidly locked. This is possible by using the

current source digital lock detect function.

AD9520

REFMON

STATUS

VOUT

110µA

DLD

LD PIN

COMPARATOR

Figure 45. Current Source Digital Lock Detect

The current source lock detect provides a current of 110 µA when

DLD is true and shorts to ground when DLD is false. If a capacitor

is connected to the LD pin, it charges at a rate determined by the

current source during the DLD true time but is discharged nearly

instantly when DLD is false. By monitoring the voltage at the

LD pin (top of the capacitor), LD = high happens only after the

DLD is true for a sufficiently long time. Any momentary DLD

false resets the charging. By selecting a properly sized capacitor,

it is possible to delay a lock detect indication until the PLL is

stably locked and the lock detect does not chatter.

To use current source digital lock detect, do the following:

•

Place a capacitor to ground on the LD pin.

•

Set Register 0x01A[5:0] = 0x04.

•

Enable the LD pin comparator (Register 0x01D[3] = 1b).

The LD pin comparator senses the voltage on the LD pin, and the

comparator output can be made available at the REFMON pin

control (Register 0x01B[4:0]) or the STATUS pin control (Register

0x017[7:2]). The internal LD pin comparator trip point and

hysteresis are given in Table 17. The voltage on the capacitor can

also be sensed by an external comparator that is connected to

the LD pin. In this case, enabling the on-board LD pin comparator

is not necessary.

The user can asynchronously enable individual clock outputs only

when CSDLD is high. To enable this feature, set the appropriate bits

in the enable output on the CSDLD registers (Register 0x0FC and

Register0x0FD).

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