AD9520-1SLASHPCBZ datasheet(42/80 Pages) AD

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AD9520-1

Data Sheet

Rev. B | Page 42 of 80

The VCO calibration clock divider is set as shown in Table 54

(Register 0x018[2:1]).The calibration divider divides the PFD

frequency (reference frequency divided by R) down to the

calibration clock. The calibration occurs at the PFD frequency

divided by the calibration divider setting. Lower VCO calibration

clock frequencies result in longer times for a calibration to be done.

The VCO calibration clock frequency is given by

fCAL_CLOCK = fREFIN/(R × cal_div)

where:

fREFIN is the frequency of the REFIN signal.

R is the value of the R counter.

cal_div is the division set for the VCO calibration divider

(Register 0x018[2:1]).

Choose a calibration divider such that the calibration frequency

is less than 6.25 MHz. Table 30 shows the appropriate value for

the calibration divider.

Table 30. VCO Calibration Divider Values for Different

Phase Detector Frequencies

PFD Rate (MHz)

Recommended VCO Calibration Divider

<12

Any

12 to 25

4, 8, 16

25 to 50

8, 16

50 to 100

The VCO calibration takes 4400 calibration clock cycles. Therefore,

the VCO calibration time in PLL reference clock cycles is given by

Time to Calibrate VCO =

4400 × R × cal_div PLL Reference Clock Cycles

Table 31. Example Time to Complete a VCO Calibration

with Different fREFIN Frequencies

fREFIN (MHz)

R Divider

PFD

Time to Calibrate VCO

100

100 MHz

88 µs

1 MHz

8.8 ms

100

100 kHz

88 ms

A VCO calibration must be manually initiated, which allows for

flexibility in deciding what order to program registers and when

to initiate a calibration, instead of having it occur every time the

values of certain PLL registers change. For example, this allows

for the VCO frequency to be changed by small amounts without

having an automatic calibration occur each time; this should be

done with caution and only when the user knows the VCO control

voltage will not exceed the nominal best performance limits. For

example, a few 100 kHz steps are fine, but a few MHz may not be.

In addition, because the calibration procedure results in rapid

changes in the VCO frequency, the distribution section is

automatically placed in SYNC until the calibration is finished.

Therefore, this temporary loss of outputs must be expected.

A VCO calibration should be initiated in the following conditions:

•

After changing any of the PLL R, P, B, and A divider settings,

or after a change in the PLL reference clock frequency.

This, in effect, means any time a PLL register or reference

clock is changed such that a different VCO frequency results.

•

When system calibration is desired. The VCO is designed to

operate properly over extremes of temperature even when

it is first calibrated at the opposite extreme. However, a

VCO calibration can be initiated at any time, if desired.

ZERO DELAY OPERATION

Zero delay operation aligns the phase of the output clocks with

the phase of the external PLL reference input. There are two zero

delay modes on the AD9520-1: internal and external.

Internal Zero Delay Mode

The internal zero delay function of the AD9520-1 is achieved by

feeding the output of Channel Divider 0 back to the PLL N

divider. In Figure 49, the change in signal routing for internal

zero delay mode is shown in blue.

Set Register 0x01E[2:1] = 01b to select internal zero delay mode.

In the default internal zero delay mode, the output of Channel

Divider 0 is routed back to the PLL (N divider) through MUX3

and MUX1 (feedback path shown in blue in Figure 49). The PLL

synchronizes the phase/edge of the output of Channel Divider 0

with the phase/edge of the reference input. External zero delay

mode must be used if Channel Divider 1, Channel Divider 2, or

Channel Divider 3 is to be used for zero delay feedback. This is

accomplished by changing the value in Register 0x01E[4:3].

Because the channel dividers are synchronized to each other,

the outputs of the channel divider are synchronous with the

reference input. Both the R delay and the N delay inside the PLL

can be programmed to compensate for the propagation delay

from the output drivers and PLL components to minimize the

phase offset between the clock output and the reference input to

achieve zero delay.

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