AD9520-1SLASHPCBZ datasheet(45/80 Pages) AD

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Data Sheet

AD9520-1

Rev. B | Page 45 of 80

The channel dividers feeding the output drivers contain one

2-to-32 frequency divider. This divider provides for division-by-1

to division-by-32. Division-by-1 is accomplished by bypassing

the divider. The dividers also provide for a programmable duty

cycle, with optional duty-cycle correction when the divide ratio

is odd. A phase offset or delay in increments of the input clock

cycle is selectable. The channel dividers operate with a signal of up

to 1600 MHz at their inputs across all channel divider ratios. The

features and settings of the dividers are selected by programming

the appropriate setup and control registers (see Table 50 through

Table 61).

VCO Divider

The VCO divider provides frequency division between the internal

VCO or the external CLK input and the clock distribution channel

dividers. The VCO divider can be set to divide by 1, 2, 3, 4, 5, or 6

(see Register 0x1E0[2:0]). However, when the VCO divider is

set to 1, none of the channel output dividers can be bypassed.

The VCO divider can also be set to static, which is useful for

applications where the only desired output frequency is the VCO

frequency. Making the VCO divider static increases the wide

band spurious-free dynamic range (SFDR). If the VCO divider

is static during VCO calibration, there is no output signal.

Therefore, it is important to calibrate the VCO with the VCO

divider set to a nonstatic value during VCO calibration, and

then set the VCO divider to static when VCO calibration is

complete.

The recommended alternative to achieving the same SFDR

performance is to set the VCO divider to 1 and enable VCO

direct mode. This allows the user to program the EEPROM

with the desired values and does not require further action after

the VCO calibration is complete.

Channel Dividers

A channel divider drives each group of three LVPECL outputs.

There are four channel dividers (0, 1, 2, and 3) driving 12 LVPECL

outputs (OUT0 to OUT11). Table 35 lists the bit locations used

for setting the division and other functions of these dividers. The

division is set by the M and N values. The divider can be

bypassed (equivalent to divide-by-1, divider circuit is powered

down) by setting the bypass bit. The duty-cycle correction can

be enabled or disabled according to the setting of the disable

Divider x DCC bits.

Table 35. Setting DX for the Output Dividers

Divider

Low Cycles,

M Value Bits

High Cycles,

N Value Bits

Bypass

Bits

Disable

Divider x

DCC Bits

0x190[7:4]

0x190[3:0]

0x191[7]

0x192[0]

0x193[7:4]

0x193[3:0]

0x194[7]

0x195[0]

0x196[7:4]

0x196[3:0]

0x197[7]

0x198[0]

0x199[7:4]

0x199[3:0]

0x19A[7]

0x19B[0]

Channel Divider Maximum Frequency

The maximum frequency at which all features of the channel

divider are guaranteed to work is 1.6 GHz; this is the number that

appears elsewhere in the datasheet. The maximum frequency at

which all features of the channel divider are guaranteed to work

is 1.6 GHz; this is the number that appears elsewhere in the data

sheet. However, if the divide-by-3 and divide-by-17 settings are

avoided, the maximum channel divider input frequency is 2 GHz.

Channel Frequency Division (0, 1, 2, or 3)

For each channel (where the channel number (x) is 0, 1, 2, or 3),

the frequency division, DX, is set by the values of M and N

(four bits each, representing Decimal 0 to Decimal 15), where

Number of Low Cycles = M + 1

Number of High Cycles = N + 1

The high and low cycles are the cycles of the clock signal that are

currently routed to the input of the channel dividers (VCO divider

out or CLK).

When a divider is bypassed, DX = 1.

Otherwise, DX = (N + 1) + (M + 1) = N + M + 2. This allows

each channel divider to divide by any integer from 2 to 32.

Duty Cycle and Duty-Cycle Correction

The duty cycle of the clock signal at the output of a channel is a

result of some or all of the following conditions:

•

M and N values for the channel

•

DCC enabled/disabled

•

VCO divider enabled/bypassed

•

CLK input duty cycle (note that the internal VCO has

a 50% duty cycle)

The DCC function is enabled, by default, for each channel divider.

However, the DCC function can be disabled individually for

each channel divider by setting the disable Divider x DCC bit

for that channel.

Certain M and N values for a channel divider result in a non-

50% duty cycle. A non-50% duty cycle can also result in an even

division, if M ≠ N. The duty-cycle correction function

automatically corrects non-50% duty cycles at the channel

divider output to 50% duty cycle.

Duty-cycle correction requires the following channel divider

conditions:

•

An even division must be set as M = N.

•

An odd division must be set as M = N + 1.

When not bypassed or corrected by the DCC function, the duty

cycle of each channel divider output is the numerical value of

(N + 1)/(N + M + 2), expressed as a percent.

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