AD9520-1SLASHPCBZ datasheet(36/80 Pages) AD

36 / 80 page

AD9520-1

Data Sheet

Rev. B | Page 36 of 80

The differential reference input receiver is powered down when

the differential reference input is not selected or when the PLL

is powered down. The single-ended buffers power down when

the PLL is powered down or when their respective individual

power-down registers are set. When the differential mode is

selected, the single-ended inputs are powered down.

In differential mode, the reference input pins are internally self-

biased so that they can be ac-coupled via capacitors. It is possible to

dc couple to these inputs. If the differential REFIN is driven by

a single-ended signal, the unused side (REFIN) should be

decoupled via a suitable capacitor to a quiet ground. Figure 43

shows the equivalent circuit of REFIN.

REF1

REF2

REFIN

150Ω

10kΩ

12kΩ

10kΩ

REFIN

85kΩ

Figure 43. REFIN Equivalent Circuit for Non-XTAL Mode

Crystal mode is nearly identical to differential mode. The user

enables a maintaining amplifier by setting the enable XTAL

OSC bit and putting a series resonant, AT fundamental cut

crystal across the REFIN and REFIN pins.

Reference Switchover

The AD9520-1 supports dual single-ended CMOS inputs, as

well as a single differential reference input. In the dual single-

ended reference mode, the AD9520-1 supports automatic

revertive and manual PLL reference clock switching between

REF1 (on Pin REFIN) and REF2 (on Pin REFIN). This feature

supports networking and other applications that require smooth

switching of redundant references. When used in conjunction

with the automatic holdover function, the AD9520-1 can

achieve a worst-case reference input switchover with an output

frequency disturbance as low as 10 ppm.

The AD9520-1 features a dc offset option in single-ended mode.

This option is designed to eliminate the risk of the reference

inputs chattering when they are ac-coupled and the reference clock

disappears. When using the reference switchover, the single-ended

reference inputs should be dc-coupled CMOS levels (with the

AD9520-1 dc offset feature disabled). Alternatively, the inputs can

be ac-coupled and dc offset feature enabled. Keep in mind,

however, that the minimum input amplitude for the reference

inputs is greater when the dc offset is turned on.

Reference switchover can be performed manually or automatically.

Manual switchover is performed either through Register 0x01C

or by using the REF_SEL pin. Manual switchover requires the

presence of a clock on the reference input that is being switched

to; otherwise, the deglitching feature must be disabled in Bit 7

of Register 0x01C. The reference switching logic fails if this

condition is not met, and the PLL does not reacquire.

Automatic revertive switchover relies on the REFMON pin to

indicate when REF1 disappears. By programming Register 0x01B =

0xF7 and Register 0x01C = 0x26, the REFMON pin is programmed

to be high when REF1 is invalid, which commands the switch to

REF2. When REF1 is valid again, the REFMON pin goes low, and

the part again locks to REF1. The STATUS pin can also be used

for this function, and REF2 can be used as the preferred reference.

A switchover deglitch feature ensures that the PLL does not

receive rising edges that are far out of alignment with the newly

selected reference. For the switchover deglitch feature to work

correctly, the presence of a clock is required on the reference input

that is being switched to. The deglitching feature can also be

disabled (Register 0x01C[7]).

Automatic nonrevertive switching is not supported.

Reference Divider R

The reference inputs are routed to the reference divider, R. R is

a 14-bit counter that can be set to any value from 0 to 16,383 by

writing to Register 0x011 and Register 0x012 (both R = 0 and R = 1

give divide-by-1.) The output of the R divider goes to one of the

PFD inputs to be compared with the VCO frequency divided by

the N divider. The frequency applied to the PFD must not exceed

the maximum allowable frequency, which depends on the

antibacklash pulse setting (see Table 2).

The R divider has its own reset. The R divider can be reset using

the shared reset bit of the R, A, and B counters. It can also be

reset by a SYNC operation.

VCO/VCXO Feedback Divider N—P, A, and B

The N divider is a combination of a prescaler, P, and two counters,

A and B. The total divider value is

N = (P × B) + A

where P can be 2, 4, 8, 16, or 32.

AD9520-1/PCBZ датащи(PDF) 36 Page - Analog Devices

AD9520-1/PCBZ датащи(HTML) 36 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

датащи скачать

ссылки URL