AD9520-1SLASHPCBZ datasheet(43/80 Pages) AD

43 / 80 page

Data Sheet

AD9520-1

Rev. B | Page 43 of 80

DIVIDE BY 1,

2, 3, 4, 5, OR 6

CLK/CLK

DIVIDER

DELAY

DIVIDER

DELAY

PFD

LOOP

FILTER

MUX1

REG 0x01E[1] = 1

REFIN/

REFIN

REG 0x01E[2]

ZERO DELAY

INTERNAL FEEDBACK PATH

EXTERNAL FEEDBACK PATH

ZERO DELAY FEEDBACK CLOCK

CHANNEL DIVIDER 0

CHANNEL DIVIDER 1

CHANNEL DIVIDER 2

CHANNEL DIVIDER 3

OUT0 TO OUT2

OUT3 TO OUT5

OUT6 TO OUT8

OUT9 TO OUT11

AD9520

Figure 49. Zero Delay Function

External Zero Delay Mode

The external zero delay function of the AD9520-1 is achieved

by feeding one clock output back to the CLK input and

ultimately back to the PLL N divider. In Figure 49, the change in

signal routing for external zero delay mode is shown in red.

Set Register 0x01E[2:1] = 11b to select external zero delay mode.

In external zero delay mode, one of the twelve output clocks

(OUT0 to OUT11) can be routed back to the PLL (N divider)

through the CLK/CLK pins and through MUX3 and MUX1.

This feedback path is shown in red in Figure 49.

For VCO calibration to work correctly, the user must specify

which channel divider is used for external zero delay mode.

Channel Divider 0 is the default. Change the value in Register

0x01E[4:3] to select Channel Divider 1, Channel Divider 2, or

Channel Divider 3 for zero delay feedback.

The PLL synchronizes the phase/edge of the feedback output

clock with the phase/edge of the reference input. Because the

channel dividers are synchronized to each other, the clock outputs

are synchronous with the reference input. Both the R delay and

the N delay inside the PLL can be programmed to compensate

for the propagation delay from the PLL components to minimize

the phase offset between the feedback clock and the reference input.

CLOCK DISTRIBUTION

A clock channel consists of three LVPECL clock outputs or six

CMOS clock outputs that share a common divider. A clock

output consists of the drivers that connect to the output pins.

The clock outputs have either LVPECL or CMOS at the pins.

The AD9520-1 has four clock channels. Each channel has its own

programmable divider that divides the clock frequency applied to

its input. The channel dividers can divide by any integer from

1 to 32.

The AD9520-1 features a VCO divider that divides the VCO

output by 1, 2, 3, 4, 5, or 6 before going to the individual channel

dividers.

The VCO divider has two purposes. The first is to limit the

maximum input frequency of the channel dividers to 1.6 GHz.

The other is to allow the AD9520-1 to generate even lower

frequencies than would be possible with only a simple post divider.

External clock signals connected to the CLK input can also use

the VCO divider.

The channel dividers allow for a selection of various duty cycles,

depending on the currently set division. That is, for any specific

division, D, the output of the divider can be set to high for N + 1

input clock cycles and low for M + 1 input clock cycles (where

D = N + M + 2). For example, a divide-by-5 can be high for one

divider input cycle and low for four cycles, or a divide-by-5 can

be high for three divider input cycles and low for two cycles.

Other combinations are also possible.

The channel dividers include a duty-cycle correction function

that can be disabled. In contrast to the selectable duty cycle

just described, this function can correct a non-50% duty cycle

caused by an odd division. However, this requires that the

division be set by M = N + 1.

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