AD9520-1SLASHPCBZ datasheet(77/80 Pages) AD

77 / 80 page

Data Sheet

AD9520-1

Rev. B | Page 77 of 80

APPLICATIONS INFORMATION

FREQUENCY PLANNING USING THE AD9520-1

The AD9520-1 is a highly flexible PLL. When choosing the PLL

settings and version of the AD9520-1, keep in mind the

following guidelines.

The AD9520-1 has four frequency dividers: the reference (or R)

divider, the feedback (or N) divider, the VCO divider, and the

channel divider. When trying to achieve a particularly difficult

frequency divide ratio requiring a large amount of frequency

division, some of the frequency division can be done by either

the VCO divider or the channel divider, thus allowing a higher

phase detector frequency and more flexibility in choosing the

loop bandwidth.

Within the AD9520-1 family, lower VCO frequencies generally

result in slightly better jitter. The difference in integrated jitter

(from 12 kHz to 20 MHz offset) for the same output frequency is

usually less than 150 fs over the entire VCO frequency range

(1.4 GHz to 2.95 GHz) of the AD9520-1 family. If the desired

frequency plan can be achieved with a version of the AD9520-1

that has a lower VCO frequency, choosing the lower frequency

part results in the best phase noise and the lowest jitter. However,

choosing a higher VCO frequency can result in more flexibility

in frequency planning.

When determining a starting point, choosing a nominal charge

pump current in the middle of the allowable range allows the

designer to increase or decrease the charge pump current and,

thus, allows fine-tuning of the PLL loop bandwidth in either

direction.

Analog Devices has an AD9520 configuration tool that can

determine the best PLL configuration, based on the user’s input

and output frequencies. It can also design the loop filter based

on user requirements.

In addition to the configuration tool, ADIsimCLK is a powerful

PLL modeling tool and a very accurate tool for determining the

optimal loop filter for a given application.

USING THE AD9520-1 OUTPUTS FOR ADC CLOCK

APPLICATIONS

Any high speed ADC is extremely sensitive to the quality of

the AD9520-1 sampling clock. An ADC can be thought of as a

sampling mixer; and any noise, distortion, or time jitter on the

clock is combined with the desired signal at the analog-to-

digital output. Clock integrity requirements scale with the analog

input frequency and resolution, with higher analog input

frequency applications at ≥14-bit resolution being the most

stringent. The theoretical SNR of an ADC is limited by the ADC

resolution and the jitter on the sampling clock.

Considering an ideal ADC of infinite resolution where the step

size and quantization error can be ignored, the available SNR

can be expressed, approximately, by the following equation:













SNR

log

(dB)

where:

fA is the highest analog frequency being digitized.

tJ is the rms jitter on the sampling clock.

Figure 70 shows the required sampling clock jitter as a function

of the analog frequency and effective number of bits (ENOB).

fA (MHz)

100

110

J = 100f

J = 200f

J = 400f

J = 1p

J = 2p

J = 10p

SNR = 20log

2πfAtJ

Figure 70. SNR and ENOB vs. Analog Input Frequency

For more information, see the AN-756 Application Note,

Sampled Systems and the Effects of Clock Phase Noise and Jitter;

and the AN-501 Application Note, Aperture Uncertainty and

ADC System Performance.

Many high performance ADCs feature differential clock inputs

to simplify the task of providing the required low jitter clock on

a noisy PCB. Distributing a single-ended clock on a noisy PCB

can result in coupled noise on the sampling clock. Differential

distribution has inherent common-mode rejection that can

provide superior clock performance in a noisy environment.

The differential LVPECL outputs of the AD9520-1 enable clock

solutions that maximize converter SNR performance.

The input requirements of the ADC (differential or single-ended,

logic level termination) should be considered when selecting the

best clocking/converter solution.

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