CS43L36 datasheet(29/89 Pages) CIRRUS

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DS1081F3

CS43L36

4.4 Clocking Architecture

4.4.1

Start-Up Clocking Using the RC Oscillator (RCO)

At power on, an integrated low-power RCO, shown in Fig. 4-11, functions as the default clock for the digital core of the

CS43L36, during which time SCLK is unavailable. A reset event always returns it to running off of the RCO. If SCLK is

unavailable, RCO clocking must be used only for I2C functionality.

RCO is multiplexed with MCLKINT and fed to the I2C slave control port. The SCLK must become active and the RCO must

be disabled before data conversion.

Note the following:

• OSC_SW_SEL_STAT (see p. 63) indicates the status of the clock switching (in transition, RCO, or SCLK/PLL). With

the existing encoding, only one bit can physically change at a time, and the bit changing is always synchronous to

the clock that is currently selected.

• OSC_PDNB_STAT (see p. 63) indicates the RCO power-down status.

• SCLK_PRESENT is used to determine the internal MCLK source. See Section 7.2.4 for details.

The clock-switch state machine uses the transition of SCLK_PRESENT to both initiate switches between the selected

internal MCLK between the SCLK pin (SCLK_PRESENT = 1) or the internal RCO (SCLK_PRESENT = 0) and to send the

I2C stop condition that each switching event requires. During switching, a delay of at least 150

S is needed before

additional successful I2C communication can begin to use the new clocking source.

Notes:

• Muting the system is recommended when a new clock source is chosen.

• For normal operation, SCLK—not RCO—must be used (SCLK_PRESENT = 1) for running the ASP data path.

4.4.1.1 Switching from RCO

With SCLK running, an SCLK_PRESENT 0-to-1 transition starts a switch from the RCO to the selected SCLK or PLL. This

switch is superseded by any outstanding I2C transactions. After the I2C stop condition is sent, the transition begins, taking

150

s to complete, during which time the system requires that no new I2C transactions be initiated. The next I2C

transaction can begin after this 150-

s delay.

4.4.1.2 Switching to RCO

To stop SCLK, the system must revert to RCO clocking to ensure that I2C communications function properly. To power

the RCO back up, SCLK_PRESENT must be cleared before stopping SCLK. A 1-to-0 SCLK_PRESENT transition

generates a glitch-free mux switch timing from SCLK to RCO. SCLK must remain running during the transition and new

I2C transactions must not be initiated for at least 150

s after an I2C stop is received. The next I2C transaction cannot

begin until after this 150-

s delay.

Failure to account for this could cause communications to fail.

4.4.2

MCLKINT Sources

The MCLKINT source is supplied directly from ASP_SCLK input pin or from the fractional-N PLL. MCLKDIV must be set

according to the MCLKINT frequency, which must be set to either the 12-MHz region (11.2896–12.288 MHz) or the 24-MHz

region (22.5792–24.576 MHz). Table 4-4 shows several examples. Table 4-2 lists further restrictions.

MCLKINT is switched through internal glitchless clock muxing. Doing so during operation may cause audible artifacts, but

does not put the device into an unrecoverable state. Therefore, it is recommended to mute the system for at least 150

s.

Table 4-2. MCLKINT Source Restrictions

MCLKINT Source MCLK_SRC_SEL (see p. 64) MCLKDIV (see p. 64)

Nominal ASP_SCLK Pin Frequency

ASP_SCLK

12 MHz

24 MHz

Fractional-N PLL

12 MHz

24 MHz

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