CS43L36 datasheet(48/89 Pages) CIRRUS

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DS1081F3

CS43L36

5 System Applications

To clear status bits set due to initiation of a path or block, the status bits must be read after the corresponding module is

enabled and before normal operation begins. Otherwise, unmasking previously set status bits causes assertion of INT.

As Table 4-16 indicates, interrupt sources are categorized into two groups:

• Condition-based interrupt source bits are set when the condition is present and they remain set until the register is

read and the condition that caused the bit to assert is no longer present.

• Event-based interrupt source bits are cleared when read. In the absence of subsequent source events, reading one

of these status bits returns a 0.

5 System Applications

This section provides recommended procedures and instruction sequences for standard operations.

5.1 Power-Up Sequence

Ex. 5-1 is the procedure for implementing HP playback from the ASP. This example sequence configures the CS43L36

for SCLK = 12.288 MHz, LRCK = 48 kHz, and TDM playback, in Slave Mode.

Table 4-15. Interrupt Status Registers and Corresponding Mask Registers—0x13

Interrupt Source Status Register

Interrupt Mask Register

SRC Interrupt Status (Section 7.4.2)

ASP RX Interrupt Status (Section 7.4.3)

DAC Interrupt Status (Section 7.4.4)

Detect Interrupt Status 1 (Section 7.4.5)

SRC Partial Lock Interrupt Status (Section 7.4.6)

VP Monitor Interrupt Status (Section 7.4.7)

PLL Lock Interrupt Status (Section 7.4.8)

SRC Interrupt Mask (Section 7.4.11)

ASP RX Interrupt Mask (Section 7.4.12)

DAC Interrupt Mask (Section 7.4.13)

Detect Interrupt Mask 1 (Section 7.7.5)

SRC Partial Lock Interrupt Mask (Section 7.4.14)

VP Monitor Interrupt Mask (Section 7.4.15)

PLL Lock Mask (Section 7.4.16)

Table 4-16. Interrupt Source Types

Group

Status Registers

Interrupt Source Type

Tip sense debounce (see Section 7.2.7) TS_UNPLUG_DBNC

TS_PLUG_DBNC

Event

Channel Overflow Interrupt

(see Section 7.4.1

)

CHA_OVFL

CHB_OVFL

Event

Serial port

(see Section 7.4.2, Section 7.4.3

)

ASPRX_OVLD

ASPRX_ERROR

ASPRX_LATE

ASPRX_EARLY 1

ASPRX_NOLRCK 1

SRC_IUNLK

SRC_ILK

1.Reading this bit following an early LRCK/SM error/no LRCK returns a 1. Subsequent reads return a 0. Valid LRCK transitions or exiting the transmit

overflow condition rearms the detection of the corresponding event. See Table 4-9 for details.

Event

Condition

Global (see Section 7.4.4

)

PDN_DONE

Condition

Headset (see Section 7.4.5)

TIP_SENSE_PLUG

TIP_SENSE_UNPLUG

All are events.

DAC (see Section 7.4.6

)

DAC_LK

Condition

VP monitor (see Section 7.4.7

)

VPMON_TRIP

Condition

PLL (see Section 7.4.8

)

PLL_LOCK

Condition

Tip sense plug/unplug status (see

Section 7.4.9

)

TS_UNPLUG

TS_PLUG

Events. Although a true event interrupt

clears when read, these dynamically reflect

the state of the debounced input signal.

Example 5-1. Power-Up Sequence

STEP

TASK

VALUE

DESCRIPTION

Apply all relevant power supplies, then assert RST before applying SCLK and LRCK to the CS43L36.

Wait 2.5 ms.

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