CS43L36 datasheet(64/89 Pages) CIRRUS

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DS1081F3

CS43L36

7.3 Clocking Registers

7.2.7

Tip Sense Indicator Status

Address 0x1115

R/O

7654321

—

TS_UNPLUG_

DBNC

TS_PLUG_

DBNC

—

Default

0000

Bits

Name

Description

7:4

—

Reserved

3TS_

UNPLUG_

DBNC

Tip sense unplug debounce status. See Section 4.8.3 for details. Setting TS_INV reverses the meaning of this bit.

0 Condition is not present.

1 Condition is present.

2TS_PLUG_

DBNC

Tip sense plug debounce status. See Section 4.8.3 for details. Setting TS_INV reverses the meaning of this bit.

0 Condition is not present.

1 Condition is present.

1:0

—

Reserved

7.3.1

MCLK Source Select

Address 0x1201

R/W

7654

321

—

MCLKDIV

MCLK_SRC_SEL

Default

00000

Bits

Name

Description

7:2

—

Reserved

MCLKDIV Master clock divide ratio. Selects the divide ratio between the selected MCLK source and the MCLKINT. Section 4.4.2 lists

supported MCLK rates and their associated programming settings.

0 (Default) Divide by 1 (source MCLKINT = ~12 MHz).

1 Divide by 2 (source MCLKINT = ~24 MHz)

Note: Change this field only if PDN_ALL = 1.

0MCLK_

SRC_

SEL

Master clock source select. Selects the internal master clock source. For programming details and examples, see Section 4.4.

0 (Default) SCLK pin

1PLL clock

7.3.2

FSYNC Pulse Width, Lower Byte

Address 0x1203

R/W

76543210

FSYNC_PULSE_WIDTH_LB

Default

000000

Bits

Name

Description

7:0

FSYNC_

PULSE_

WIDTH_

FSYNC pulse width LB. FSYNC_PULSE_WIDTH_UB | FSYNC_PULSE_WIDTH_LB provides an 11-bit field to set the duty

cycle of LRCK in Hybrid-Master Mode. These combined value forms an integer number of SCLK periods within an LRCK

frame that governs the LRCK high time. See Section 4.5.2 for usage details and Section 5 for a programming example. The

value must be 1 less than the desired width of the LRCK pulse, measured in SCLK counts, as illustrated by the value below.

FSYNC_PULSE_WIDTH_UB | FSYNC_PULSE_WIDTH_LB yield the following setting value:

000 0000 0000 (Default) LRCK is one SCLK wide.

7.3.3

FSYNC Pulse Width, Upper Byte

Address 0x1204

R/W

76543210

—

FSYNC_PULSE_WIDTH_UB

Default

000000

Bits

Name

Description

7:3

—

Reserved

2:0

FSYNC_PULSE_

WIDTH_UB

FSYNC pulse width UB. See description for FSYNC_PULSE_WIDTH_LB in Section 7.3.2.

000 (Default)

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