CS43L36 datasheet(10/89 Pages) CIRRUS

10 / 89 page

DS1081F3

CS43L36

2 Typical Connections

Figure 2-1. Typical Connection Diagram

Notes:

1. RP_I and RP_W values can be determined by the INT and WAKE pin specifications in Table 3-14.

2. HPSENSA and HPSENSB are supported only on the WLCSP package.

3. RP_I2C values can be determined by the I2C pull-up resistance specification in Table 3-13.

4. The headphone amplifier’s output power and distortion ratings use the nominal capacitances shown. Larger capacitance reduces ripple on

the internal amplifiers’ supplies and, in turn, reduces distortion at high-output power levels. Smaller capacitance may not reduce ripple

enough to achieve output power and distortion ratings. Because actual values of typical X7R/X5R ceramic capacitors deviate from nominal

values by a percentage specified in the manufacturer’s data sheet, capacitors must be selected for minimum output power and maximum

distortion required. Higher value capacitors than those shown may be used, however lower value capacitors must not (values can vary from

the nominal by ±20%). See Section 2.1.2 for additional details.

5. Series resistance in the path of the power supplies must be avoided. Any voltage drop on VCP directly affects the negative charge-pump

supply (–VCP_FILT) and clips the audio output.

6. Lowering capacitance below the value shown affects PSRR, THD+N performance, and interchannel isolation and intermodulation.

2.2 µF

FLYC

FLYN

2.2 µF

FLYP

2.2 µF

+VCP_FILT

–VCP_FILT

2.2 µF

GNDCP

All external passive component

values shown are nominal.

Key for Capacitor Types Required:

Use low ESR, X7R/X5R capacitors

** Use C0G or NPO capacitors

If no type symbol is shown next to a

capacitor, any type may be used.

FILT+

10 µF

4.7 µF

ASP_LRCK/FSYNC

ASP_SCLK

ASP_SDIN

GNDA

SDA

SCL

WAKE

INT

RESET

VCP

VD_FILT

See

DIGLDO_PDN

and VL_SEL

Configurations

DIGLDO_PDN

AD0

GNDL

AD1

2.2 µF

VL_SEL

GNDD

TIP_SENSE

HS3

Headset Connector

Headphone

Output Filter

HS3_REF

GNDHS

To External

Microphone Input

and Bias Circuitry

(AFE/PGA + ADC)

DIGLDO_PDN and VL_SEL Configurations

DIGLDO_PDN = 0 (GNDD)

VD_FILT

1 µF

1.8 V

DIGLDO_PDN

0.1 µF

1.2 V

VL_SEL

Battery

(VP = 3.0 to 5.0V)

VL_SEL = 1 (3.0 to 5.0 V)

DIGLDO_PDN = 0 (GNDD)

VD_FILT

1 µF

1.2 V

DIGLDO_PDN

0.1 µF

VL_SEL

VL_SEL = 0 (GNDD)

DIGLDO_PDN = 1 (3.0 to 5.0 V)

VD_FILT

DIGLDO_PDN

0.1 µF

1.8 V

VL_SEL = 1 (3.0 to 5.0 V)

VL_SEL

Battery

(VP = 3.0 to 5.0V)

TSTI

TSTO

RP_I

RP_I2C

RP_W

Applications

Processor

PMU

Battery

(3.0–5.0 V)

1.8 V

1.8 V/1.2 V

VL or VP

HPOUTB

HPOUTA

HPSENSB

HPSENSA

CS43L36

Note 1

Note 4

Note 5

Note 6

Note 1

Note 3

Note: The headset GND

connection must be made

via the HS3 and HS3_REF

connections and not to the

PCB GND.

Note 2

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