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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS43L36 датащи(PDF) 78 Page - Cirrus Logic |
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CS43L36 датащи(HTML) 78 Page - Cirrus Logic |
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78 / 89 page  DS1081F3 78 CS43L36 7.13 SRC Registers 7.13 SRC Registers 7.14 Serial Port Receive Registers 7.12.3 Serial Port Receive Sample Rate Address 0x2503 R/W 76543210 — SP_RX_FS Default 100011 00 Bits Name Description 7:5 — Reserved 4:0 SP_ RX_ FS SP receive sample rate. Configures the sample rate of the SRC FSI when in Isochronous Mode. This setting autoscales when configuring for a isochronous rate of 96 or 192 kHz with respect to the 48-kHz isochronous rate, e.g., 24-kHz setting in isochronous rate of 48 kHz would be scaled to a 48-kHz setting in isochronous rate of 96 kHz. 0 0000 Reserved 0 0001 8.00 kHz 0 0010 11.025 kHz 0 0011 11.0295 kHz 0 0100 12.000 kHz 0 0101 16.000 kHz 0 0110 22.050 kHz 0 0111 22.059 kHz 0 1000 24.000 kHz 0 1001 32.000 kHz 0 1010 44.100 kHz 0 1011 44.118 kHz 0 1100 (Default) 48.000 kHz 0 1101 88.200 kHz 0 1110 88.236 kHz 0 1111 96.000 kHz 1 0000 176.400 kHz 1 0001 176.472 kHz 1 0010 192.000 kHz 1 0011–1 1111 Reserved 7.13.1 SRC Input Sample Rate Address 0x2601 R/W 76543210 — SRC_SDIN_FS Default 010000 00 Bits Name Description 7:5 — Reserved 4:0 SRC_ SDIN_ FS SRC input sample rate. Must equal FsINT if SRC_BYPASS_DAC =1. 0 0000 (Default) Don’t know 0 0001 8.00 kHz 0 0010 11.025 kHz 0 0011 11.0295 kHz 0 0100 12.000 kHz 0 0101 16.000 kHz 0 0110 22.050 kHz 0 0111 22.059 kHz 0 1000 24.000 kHz 0 1001 32.000 kHz 0 1010 44.100 kHz 0 1011 44.118 kHz 0 1100 48.000 kHz 0 1101 88.200 kHz 0 1110 88.236 kHz 0 1111 96.000 kHz 1 0000 176.400 kHz 1 0001 176.472 kHz 1 0010 192.000 kHz 1 0011–1 1111 Reserved 7.14.1 ASP Receive Enable Address 0x2A01 R/W 76543210 — ASP_RX0_CH_EN — ASP_RX0_2FS Default 000000 00 Bits Name Description 7:4 — Reserved 3:2 ASP_ RX0_ CH_EN ASP receive DAI0 enable. Determines whether the channel buffer gets populated. ASP_RX0_CH_EN[0] = Channel 1 ASP_RX0_CH_EN[1] = Channel 2 0 (Default) The corresponding channel buffer does not get populated. 1 The corresponding channel buffer is populated 1— Reserved 0ASP_ RX0_ 2FS ASP receive DAI0 double-rate mode. 0 (Default) Standard sample rate, Fs (not doubled) 1 Sample rate is doubled, 2 Fs 7.14.2 ASP Receive DAI0 Channel 1 Phase and Resolution Address 0x2A02 R/W 7 6 5432 1 0 — ASP_RX0_CH1_AP — ASP_RX0_CH1_RES Default 0 0 0000 1 1 Bits Name Description 7— Reserved 6 ASP_RX0_ CH1_AP ASP receive DAI0 active phase. Valid only in 50/50 Mode (ASP_5050 = 1 and ASP_RX0_2FS = 0). 0 (Default) Low. In 50/50 Mode, channel data is valid if LRCK/FSYNC is low. 1 High. In 50/50 Mode, channel data is valid when LRCK/FSYNC is high. |
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