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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS43L36 датащи(PDF) 28 Page - Cirrus Logic |
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CS43L36 датащи(HTML) 28 Page - Cirrus Logic |
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28 / 89 page  DS1081F3 28 CS43L36 4.4 Clocking Architecture 4.3.4 HP Current Limiter The CS43L36 features built-in current-limit protection for the HP output. Table 3-8 lists the current limit threshold during the short-circuit conditions shown in Fig. 4-10. For HP amplifiers, current is from the internal charge-pump output, and, as such, applies the current from VCP or VP, depending on the mode. Figure 4-10. HP Short-Circuit Setup 4.4 Clocking Architecture The CS43L36 offers several ways to support control, ASP operation, data conversion, and signal processing. Internal clocks are generated either from SCLK (ASP_SCLK) or from the integrated fractional-N PLL; see Fig. 4-11. Depending on the MCLK_SRC_SEL setting (see Fig. 4-12), MCLKINT is provided by one of the following methods: • Externally sourced directly from the ASP_SCLK input pin • Internally generated from an integrated fractional-N PLL with ASP_SCLK as a reference clock Figure 4-11. Clock Architecture Block Diagram VP VCP Charge Pump LDO VP_CP GNDA/GNDCP HPOUTA HPOUTB I I Digital Core CCM Digital Clock Generation Delay Analog Core ASP_SCLK SCL Predivide 24/12 MHz Analog Clock Generation Control Port/APB Clock Generation ASP Clock Generation FSYNC Generation ASP_LRCK/ FSYNC DAC analog clock MCLKINT RESET PLL RCO PoR GFM X 2 VD_FILT VP VL * Use the RCO for I2C functionality only if SCLK is unavailable. * |
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