CS43L36 datasheet(51/89 Pages) CIRRUS

51 / 89 page

DS1081F3

CS43L36

5.3 Page 0x30 Read Sequence

The following sequence is required to read from Page 0x30:

1. Power up Page 0x30 by clearing bit 7 of register 0x1102.

2. Enable Page 0x30 reads by writing the value 0x01 to register 0x1801.

3. Perform the read from Page 0x30.

5.4 PLL Clocking

Data-path logic is in the MCLK domain, where SCLK is expected to be 12 or 24 MHz. For clocking scenarios where ASP_

SCLK is neither 12 nor 24 MHz, the PLL must be turned on to provide the desired internal MCLK. At startup, the system

sets the SCLK bypass as default mode and switches to PLL output after it settles. PLL start-up time is a maximum of 1 ms.

5.5 VD_FILT/VL ESD Diode

Note the following:

• If VD_FILT is supplied externally, VL must be supplied before VD_FILT.

• If the internal LDO is enabled, it generates VD_FILT from VL.

• If the LDO is disabled (DIGLDO_PDN asserted) and VD_FILT is supplied externally; however, the LDO diode could

be forward biased in cases where VD_FILT is supplied first.

• If the LDO is disabled and VD_FILT and VL are respectively powered via separate 1.2- and 1.8-V supplies, it is

recommended to have an ESD diode between VD_FILT and VL.

2 Power down the HP

amplifier.

Power Down Control 1. 0x1101

0xFE

Reserved

ASP_DAI_PDN

MIXER_PDN

Reserved

HP_PDN

Reserved

PDN_ALL

—

ASP input path is powered down

Mixer is powered down

—

HPOUT powered down

—

DAC powered up

3 Power down the ASP and

SRC.

Power Down Control 2. 0x1102

0x8C

Reserved

DISCHARGE_FILT+

SRC_PDN_OVERRIDE

Reserved

DAC_SRC_PDNB

Reserved

100

—

FILT+ is not clamped to ground.

SRC is powered down.

—

DAC SRC is powered down.

—

4 Power down the DAC.

Power Down Control 1. 0x1101

0xFF

Reserved

ASP_DAI_PDN

MIXER_PDN

Reserved

HP_PDN

Reserved

PDN_ALL

—

ASP input path is powered down

Mixer is powered down

—

HPOUT powered down

—

DAC powered down.

5 Read PDN_DONE to

confirm that the DAC is

completely powered down.

DAC Interrupt Status

. 0x1308

0x01

Reserved

PDN_DONE

0000 000

—

Power-down done.

6 Repeat Step 5 until the PDN_DONE status bit indicates the DAC has powered down.

7 Discharge the capacitor

attached to the FILT+ pin.

Power Down Control 2. 0x1102

0x9C

Reserved

DISCHARGE_FILT+

SRC_PDN_OVERRIDE

Reserved

DAC_SRC_PDNB

Reserved

100

—

FILT+ is clamped to ground.

SRC is powered down.

—

DAC SRC is powered down.

—

8 If required, remove the SCLK signal.

9 If required, remove all relevant power supplies from the DAC.

Example 5-2. Power-Down Sequence (Cont.)

STEP TASK

VALUE

DESCRIPTION

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