CS43L36 datasheet(72/89 Pages) CIRRUS

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DS1081F3

CS43L36

7.5 Fractional-N PLL Registers

7.5.2

PLL Division Fractional Bytes 0–2

Address 0x1502–0x1504

R/W

76543210

0x1502

PLL_DIV_FRAC[7:0]

0x1503

PLL_DIV_FRAC[15:8]

0x1504

PLL_DIV_FRAC[23:16]

Default

000000

Bits

Name

Description

7:0

PLL_DIV_

FRAC[7:0]

PLL fractional portion of divide ratio LSB. See Section 4.4.3 for details. There are 3 bytes of PLL feedback divider fraction

portion: This is LSB byte; e.g., 0xFF means (2–17 +2–18 + …+2–24)

0000 0000 (Default)

7:0

PLL_DIV_

FRAC[15:8]

PLL fractional portion of divide ratio middle byte; e.g., 0xFF means (2–9 +2–10 + …+2–16). See Section 4.4.3 for details.

0000 0000 (Default)

7:0

PLL_DIV_

FRAC[23:16]

PLL fractional portion of divide ratio MSB; e.g., 0xFF means (2–1 +2–2 + …+2–8). See Section 4.4.3 for details.

0000 0000 (Default)

7.5.3

PLL Division Integer

Address 0x1505

R/W

765

43210

PLL_DIV_INT

Default

000000

Bits

Name

Description

7:0 PLL_DIV_INT PLL integer portion of divide ratio. Integer portion of PLL feedback divider. See Section 4.4.3 for details.

0100 0000 (Default)

7.5.4

PLL Control 3

Address 0x1508

R/W

7654321

PLL_DIVOUT

Default

000100

Bits

Name

Description

7:0

PLL_

DIVOUT

Final PLL clock output divide value. See Section 4.4.3 for configuration details.

0001 0000 (Default)

7.5.5

PLL Calibration Ratio

Address 0x150A

R/W

7654321

PLL_CAL_RATIO

Default

100000

Bits

Name

Description

7:0

PLL_CAL_

RATIO

PLL calibration ratio. See Section 4.4.3 for configuration details. Target value for PLL VCO calibration.

1000 0000 (Default)

7.5.6

PLL Control 4

Address 0x151B

R/W

654

—

PLL_MODE

Default

Bits Name

Description

7:2

—

Reserved

1:0

PLL_

MODE

PLL bypass mode. Configures 500/512 and 1029/1024 factor bypasses. See Section 4.4.3 for configuration details.

00 Unsupported

01 500/512 only (1029/1024 bypassed)

10 1029/1024 only (500/512 bypassed)

11 (Default) Both bypassed

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