CS43L36 datasheet(49/89 Pages) CIRRUS

49 / 89 page

DS1081F3

CS43L36

5.1 Power-Up Sequence

Power up the DAC.

Power Down Control 2. 0x1102

0x83

Reserved

DISCHARGE_FILT+

SRC_PDN_OVERRIDE

Reserved

DAC_SRC_PDNB

Reserved

100

—

FILT+ is not clamped to ground.

SRC is powered up.

—

DAC SRC is powered up.

—

Configure the device’s ASP and ASP SRC.

4.1 Configure switch

from RCO to SCLK.

Oscillator Switch Control. 0x1107

0x01

Reserved

SCLK_PRESENT

0000 000

—

SCLK is present.

4.2 Power down the

RCO.

Oscillator Switch Status. 0x1109

0x01

Reserved

OSC_PDNB_STAT

OSC_SW_SEL_STAT

0000 0

—

RCO powered down

RCO selected for internal MCLK

4.3 Configure device’s

internal sample rate

with the applied

MCLK signal.

MCLK Control. 0x1009

0x02

Reserved

INTERNAL_FS

Reserved

0000 00

—

Internal sample rate is MCLK/256= 48 kHz.

—

4.4 Select MCLK

source.

MCLK Source Select. 0x1201

0x00

Reserved

MCLKDIV

MCLK_SRC_SEL

0000 00

—

Divide by 1.

SCLK pin is MCLK source.

4.5 Configure the

FSYNC period.

FSYNC Period, Lower Byte. 0x1205

0xFF

FSYNC_PERIOD_LB

1111 1111 256 SCLKs per LRCK lower byte.

4.6 Configure the

FSYNC period.

FSYNC Period, Upper Byte. 0x1206

0x00

FSYNC_PERIOD_UB

0000 0000 0 SCLKs per LRCK upper byte

4.7 Configure FSYNC

pulse width.

FSYNC Pulse Width, Lower Byte. 0x1203

0x1F

FSYNC_PULSE_WIDTH_LB

0001 1111 LRCK is one SCLK Wide.

4.8 Configure the ASP

clock.

ASP Clock Configuration 1. 0x1207

0x00

Reserved

ASP_SCLK_EN

ASP_HYBRID_MODE

Reserved

ASP_SCPOL_IN_DAC

ASP_LCPOL_OUT

ASP_LCPOL_IN

—

ASP SCLK disabled.

LRCK is an input from an external source.

—

SCLK input drive polarity for DAC is normal.

LRCK output drive polarity is normal.

LRCK input polarity (pad to logic) is normal.

4.9 Configure the ASP

frame.

ASP Frame Configuration. 0x1208

0x10

Reserved

ASP_STP

ASP_5050

ASP_FSD

000

—

Frame begins when LRCK transitions low to high

LRCK duty cycle per FSYNC_PULSE_WIDTH_LB/UB

Zero SCLK frame start delay

4.10Configure serial port

receive channel

positions.

Serial Port Receive Channel Select. 0x2501

0x04

Reserved

SP_RX_CHB_SEL

SP_RX_CHA_SEL

0000

—

SP RX Channel B position is 1.

SP RX Channel A position is 0.

4.11Set receive sample

rate.

Serial Port Receive Sample Rate. 0x2503

0x8C

Reserved

SP_RX_FS

100

0 1100

—

SP receive sample rate = 48 kHz.

4.12Configure the SRC

sample rate

detection.

SRC Input Sample Rate. 0x2601

0x20

Reserved

SRC_SDIN_FS

0010

0000

—

ASP sample rate is autodetected.

4.13Configure Channel 2

size to 24 bits per

sample.

ASP Receive DAI0 Channel 2 Phase and Resolution.

0x2A05

0x02

Reserved

ASP_RX0_CH2_AP

Reserved

ASP_RX_CH2_RES

00 00

—

In 50/50 mode, channel data valid if LRCK is low.

—

Size is 24 bits per sample.

4.14Configure location of

the Channel 2 MSB

with respect to SOF.

ASP Receive DAI0 Channel 2 Bit Start MSB. 0x2A06

0x00

Reserved

ASP_RX0_CH2_BIT_ST_MSB

0000 000

—

ASP receive bit start MSB = 0.

4.15Configure location of

the Channel 2 LSB

with respect to SOF.

ASP Receive DAI0 Channel 2 Bit Start LSB. 0x2A07

0x18

ASP_RX0_CH2_BIT_ST_LSB

0001 1000 ASP transmit bit start LSB = 24.

Example 5-1. Power-Up Sequence (Cont.)

STEP

TASK

VALUE

DESCRIPTION

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