CS43L36 datasheet(65/89 Pages) CIRRUS

65 / 89 page

DS1081F3

CS43L36

7.3 Clocking Registers

7.3.4

FSYNC Period, Lower Byte

Address 0x1205

R/W

765

43210

FSYNC_PERIOD_LB

Default

111001

Bits

Name

Description

7:0 FSYNC_

PERIOD_

FSYNC period LB. FSYNC_PERIOD_UB | FSYNC_PERIOD_LB controls frequency (number of SCLKs per LRCK) of LRCK

for ASP. Section 4.5.2 for details on how this register is used and Section 5 for a programming example. The final SCLKs per

LRCK count is +1 of the value set in the UB|LB register field

FSYNC_PERIOD_UB | FSYNC_PERIOD_LB yield the following setting values:

0x000 1 SCLK/LRCK …

0x0F9 (Default) 250 SCLKs/ LRCK …

0xFFF 4096 SCLKs/ LRCK

7.3.5

FSYNC Period, Upper Byte

Address 0x1206

R/W

43210

—

FSYNC_PERIOD_UB

Default

00000

Bits

Name

Description

7:4

—

Reserved

3:0

FSYNC_

PERIOD_UB

FSYNC period UB. See description for FSYNC_PERIOD_LB in Section 7.3.4.

0000 (Default)

7.3.6

ASP Clock Configuration 1

Address 0x1207

R/W

—

ASP_SCLK_EN ASP_HYBRID_MODE

—

ASP_SCPOL_IN_DAC ASP_LCPOL_OUT ASP_LCPOL_IN

Default

Bits

Name

Description

7:6

—

Reserved

ASP_SCLK_

ASP SCLK enable. Must be set if DAI functionality is used.

0 (Default) Disabled

1 Enabled

4ASP_

HYBRID_

MODE

ASP Hybrid-Master Mode. Allows the internal LRCK to be generated from SCLK. See Fig. 4-15 for details.

0 (Default) LRCK is input from external source which is synchronous to SCLK (Slave Mode).

1 LRCK is an output generated from SCLK (Hybrid Master Mode).

3—

Reserved

2ASP_SCPOL_

IN_DAC

ASP SCLK input polarity. Determines the polarity for the DAC path. See Fig. 4-15 for details.

0 (Default) Normal

1Inverted

ASP_LCPOL_

OUT

ASP LRCK output drive polarity. Determines the polarity for the ASP LRCK output drive. See Fig. 4-15 for details.

0 (Default) Normal

1Inverted

ASP_LCPOL_

ASP LRCK input polarity. Determines ASP LRCK input polarity (pad to logic). See Fig. 4-15 for details.

0 (Default) Normal

1Inverted

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