CS43L36 datasheet(47/89 Pages) CIRRUS

47 / 89 page

DS1081F3

CS43L36

4.11 Reset

Figure 4-29. Control-Port Timing, I2C Reads with Preamble and Autoincrement

The following pseudocode illustrates an aborted write operation followed by a single read operation, assumes page

address has been written. For multiple read operations, autoincrement would be set to on (as shown in Fig. 4-29).

Send start condition.

Send 10010(AD1)(AD0)0 (chip address and write operation).

Receive acknowledge bit.

Send MAP byte, autoincrement off.

Receive acknowledge bit.

Send stop condition, aborting write.

Send start condition.

Send 10010(AD1)(AD0)1 (chip address and read operation).

Receive acknowledge bit.

Receive byte, contents of selected register.

Send acknowledge bit.

Send stop condition.

4.11 Reset

The CS43L36 offers the reset options described in Table 4-14.

4.12 Interrupts

The following sections describe the CS43L36 interrupt implementation.

4.12.1 Standard Interrupts

The interrupt output pin, INT, is used to signal the occurrence of events within the device’s interrupt status registers. Events

can be masked individually by setting corresponding bits in the interrupt mask registers. Table 4-15 lists interrupt status

and mask registers. The configuration of mask bits determines which events cause the immediate assertion of INT:

• When an unmasked interrupt status event is detected, the status bit is set and INT is asserted.

• When a masked interrupt status event is detected, the interrupt status bit is set, but INT is not affected.

Once asserted, INT remains asserted until all status bits that are unmasked and set have been read. Interrupt status bits

are sticky and read-to-clear: Once set, they remain set until the register is read and the associated interrupt condition is

not present. If a condition is still present and the status bit is read, although INT is deasserted, the status bit remains set.

Table 4-14. Reset Summary

Reset

Cause

Result

Device hard reset

Asserting RESET If RESET is asserted, all registers (both VP and VD_FILT domains) and all state machines are

immediately set to their defaults. No operation can begin until RESET is deasserted. Before normal

operation can begin, RESET must be asserted at least once after the VP supply is first brought up.

Power-on reset (POR) Power up

If VD_FILT is lower than the POR threshold, the VD_FILT register fields and the state machines are

held in reset, setting them to their default values/states. This does not reset the VP registers. The

POR releases the reset when the VD_FILT supply goes above the POR threshold.

VL and VA supplies must be turned at the same time the VD_FILT supply is turned on.

SCL

CHIP ADDRESS(WRITE)

MAP BYTE

DATA

START

ACK

STOP

ACK

SDA

CHIP ADDRESS(READ)

START

12 13 14 15

20 21 22 23 24

26 27 28

10 11

17 18 19

ACK

STOP

MAP Addr = Z

Addr = 10010

DATA

SDA

Source

Master

Pullup

Slave

Master

Pullup

Addr = 10010

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