CS43L36 datasheet(23/89 Pages) CIRRUS

23 / 89 page

DS1081F3

CS43L36

4.3 Class H Amplifier

2. Power down the HP block: HP_PDN = 1 (see p. 62).

3. Mute the analog outputs: ANA_MUTE_B = ANA_MUTE_A = 1 (see p. 76).

4. Disable the DAC high-pass filter: DAC_HPF_EN = 0 (see p. 76).

Note: Restore the previous setup after detection completes.

5. Set LATCH_TO_VP (see p. 74).

6. Set ADPTPWR = 100 (see p. 76).

7. Set the analog soft-ramp rate (ASR_RATE = 0111; see p. 60).

8. Set the digital soft-ramp rate (DSR_RATE; see p. 60) = 0001.

9. After load detection completes, ASR_RATE, DSR_RATE, ADPTPWR, and DAC_HPF_EN must be restored to

their previous values. See Section 4.3 for details.

After an HP-detect event, if HP_LD_EN is set (see p. 73), the CS43L36 proceeds to detect the resistance and capacitance

of the output load. A 24-kHz tone is output on HPOUTA, and HS3 is measured using an internal resistor bank as a

reference.

RLA_STAT (see p. 73) reports resistance-detection results for Channel A as follows:

• 00: 15



• 01: 30



• 10: 3 k



• 11: Reserved

If the typical output resistance of less than ~300

is indicated, a low-capacitance load is assumed. If the resistance is

greater than 300

 capacitance detection proceeds. After the detection sequence completes, HPLOAD_DET_DONE (see

p. 73) is set. The results of capacitor detection is reported in CLA_STAT (see p. 73). This result can be used to program

the value in HPOUT_LOAD(see p. 75), which determines the compensation of the headphone amplifier.

Notes:

• The HP path must be powered down before updating the HPOUT_LOAD setting and repowered afterwards.

• Low capacitance results were determined with CL = 1 nF; high capacitance results were determined with CL = 10 nF.

4.2.3

Slow Start Control

Volume control, DAC, and HP soft ramping is enabled through SLOW_START_EN (p. 61). If SLOW_START_EN = 111,

changes to DAC/HP volumes are applied slowly by stepping through each volume-control setting with a delay between

steps equal to an integer number of Fs periods. The delay between steps, which can vary from 1/Fs to 72/Fs periods, is

set via DSR_RATE and ASR_RATE (see p. 60).

If ramping is disabled, changes occur immediately with the clock edge.

4.3 Class H Amplifier

Fig. 4-5 shows the Class H operation.

Figure 4-5. Class H Operation

VCP

Class H Control

–VCP_FILT

–VCP

–VCP/2

–VCP/3

–2.5 V

+VCP_FILT

+VCP

+VCP/2

+VCP/3

+2.5 V

VP_CP

LDO Output

ADPTPWR on p. 76

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