CS43L36 datasheet(20/89 Pages) CIRRUS

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DS1081F3

CS43L36

4 Functional Description

This section provides a general description of the CS43L36 architecture and detailed functional descriptions of the various

blocks that make up the CS43L36. Fig. 4-1 shows the flow of signals through the CS43L36 and gives links to detailed

descriptions of the respective sections.

The CS43L36 is an ultralow-power stereo DAC. The DAC feeds a stereo pseudodifferential output amplifier. The

converters operate at a low oversampling ratio, maximizing power savings while maintaining high performance.

The serial data interface ports operate either at standard audio-sample rates as timing slaves or in Hybrid-Master Mode

as a bit-clock slave generating LRCK internally. An onboard fractional-N PLL can be used to generate the internal-core

timing (MCLKINT) if the SCLK source is not one of the following rates (where N =2 or 4):

• N x 5.6448 or 6.1440 MHz

• USB rates (N x 6 MHz)

The CS43L36 significantly reduces overall power consumption, with a very low-voltage digital core and with low-voltage

Class H amplifiers (powered from an integrated LDO regulator and a step-down/inverting charge pump, respectively). The

CS43L36 comprises the following subblocks:

• Volume control, described in Section 4.1, uses selectable attenuation to provide relative volume control and to avoid

clipping.

• Analog outputs. The analog output block, described in Section 4.2, includes separate pseudodifferential headphone

Class H amplifiers. An on-chip step-down/inverting charge pump creates a positive and negative voltage equal to the

input or to either one-half or one-third of the input supply for the amplifiers, allowing an adaptable, full-scale output

swing centered around ground. The resulting internal amplifier supply can be ±VCP/3, ±VCP/2, ±VCP, or ±2.5 V.

The inverting architecture eliminates the need for large DC-blocking capacitors and allows the amplifier to deliver

more power to HP loads at lower supply voltages. The step-down architecture allows the amplifier’s power supply

to adapt to the required output signal. This adaptive power-supply scheme converts traditional Class AB amplifiers

into more power-efficient Class H amplifiers.

Figure 4-1. Overview of Signal Flow

PLL

Clock

Gen

MCLK

Interpolator

and

Volume

Control

ASP_SDIN

ASP_SCLK

ASP_LRCK

/FSYNC

SCL

SDA

Pseudodifferential

Input

Headphone Detect

HS3

TIP_SENSE

INT

Digital Audio

Input

I2C Slave

SRC

Headset

Impedance

Detect and

Switches

WAKE

AD0 AD1

HS3_REF

VD_FILT

LDO

with

Bypass

DIGLDO_PDN

+VCP_FILT

–VCP_FILT

Inverting

Step-Down

LDO

Analog Core

POR

VCP

VP_CP

Digital

Core

CS43L36

Interpolator

and

Volume

Control

Multibit



Modulator

DAC

Multibit



Modulator

HPOUTB

–VCP_FILT

HPOUTA

+VCP_FILT

–VCP_FILT

+VCP_FILT

HPSENSA *

–

HPSENSB *

* WLCSP

package only

DAC

See Section 4.1.“Digital Volume Control.”

See Section 4.2 “Analog Output.”

See Section 4.7,

Headset Interface”

See Section 4.4,

“Clocking

Architecture.”

See Section 4.6,

“Sample-Rate

Converters (SRCs)”

See Section 4.10, “Control-Port Operation”

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