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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ISM330DLC датащи(PDF) 62 Page - STMicroelectronics |
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ISM330DLC датащи(HTML) 62 Page - STMicroelectronics |
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62 / 116 page  Register description ISM330DLC 62/116 DocID030686 Rev 2 10.9 DRDY_PULSE_CFG (0Bh) DataReady configuration register (r/w). Table 43. DRDY_PULSE_CFG register Table 44. DRDY_PULSE_CFG register description 10.10 INT1_CTRL (0Dh) INT1 pad control register (r/w). Each bit in this register enables a signal to be carried through INT1. The pad’s output will supply the OR combination of the selected signals. Table 45. INT1_CTRL register Table 46. INT1_CTRL register description DRDY_ PULSED 0(1) 1. This bit must be set to ‘0’ for the correct operation of the device. 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) DRDY_ PULSED Enable pulsed data-ready mode. Default value: 0 (0: Data-ready latched mode. Returns to 0 only after output data has been read; 1: Data-ready pulsed mode. The data-ready pulses are 75 μs long.) 00 INT1_FULL _FLAG INT1_ FIFO_OVR INT1_ FTH INT1_ BOOT INT1_ DRDY_G INT1_ DRDY_XL INT1_FULL_FLAG FIFO full flag interrupt enable on INT1 pad. Default value: 0 (0: disabled; 1: enabled) INT1_FIFO_OVR FIFO overrun interrupt on INT1 pad. Default value: 0 (0: disabled; 1: enabled) INT1_FTH FIFO threshold interrupt on INT1 pad. Default value: 0 (0: disabled; 1: enabled) INT1_ BOOT Boot status available on INT1 pad. Default value: 0 (0: disabled; 1: enabled) INT1_DRDY_G Gyroscope Data Ready on INT1 pad. Default value: 0 (0: disabled; 1: enabled) INT1_DRDY_XL Accelerometer Data Ready on INT1 pad. Default value: 0 (0: disabled; 1: enabled) |
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