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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ISM330DLC датащи(PDF) 61 Page - STMicroelectronics |
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ISM330DLC датащи(HTML) 61 Page - STMicroelectronics |
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61 / 116 page  DocID030686 Rev 2 61/116 ISM330DLC Register description 116 10.8 FIFO_CTRL5 (0Ah) FIFO control register (r/w). Table 40. FIFO_CTRL5 register description Table 39. FIFO_CTRL5 register 0(1) 1. This bit must be set to ‘0’ for the correct operation of the device. ODR_ FIFO_3 ODR_ FIFO_2 ODR_ FIFO_1 ODR_ FIFO_0 FIFO_ MODE_2 FIFO_ MODE_1 FIFO_ MODE_0 ODR_FIFO_[3:0] FIFO ODR selection, setting FIFO_MODE also. Default: 0000 For the configuration setting, refer to Table 41. FIFO_MODE_[2:0] FIFO mode selection bits, setting ODR_FIFO also. Default value: 000 For the configuration setting, refer to Table 42. Table 41. FIFO ODR selection ODR_FIFO_[3:0] Configuration(1) 1. If the device is working at an ODR slower than the one selected, FIFO ODR is limited to that ODR value. Moreover, these bits are effective if the DATA_VALID_SEL FIFO bit of MASTER_CONFIG (1Ah) is set to 0. 0000 FIFO disabled 0001 FIFO ODR is set to 12.5 Hz 0010 FIFO ODR is set to 26 Hz 0011 FIFO ODR is set to 52 Hz 0100 FIFO ODR is set to 104 Hz 0101 FIFO ODR is set to 208 Hz 0110 FIFO ODR is set to 416 Hz 0111 FIFO ODR is set to 833 Hz 1000 FIFO ODR is set to 1.66 kHz 1001 FIFO ODR is set to 3.33 kHz 1010 FIFO ODR is set to 6.66 kHz Table 42. FIFO mode selection FIFO_MODE_[2:0] Configuration mode 000 Bypass mode. FIFO disabled. 001 FIFO mode. Stops collecting data when FIFO is full. 010 Reserved 011 Continuous mode until trigger is deasserted, then FIFO mode. 100 Bypass mode until trigger is deasserted, then Continuous mode. 101 Reserved 110 Continuous mode. If the FIFO is full, the new sample overwrites the older one. 111 Reserved |
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