PC87413 datasheet(124/257 Pages) NSC

124 / 257 page

6.0 ACCESS.bus Interface (Continued)

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Reset Slave Transaction

This is a broadcast transaction to the General Call address (00h) that resets the ACCESS.bus Interface logic and the data

registers (the configuration registers are not affected) and reloads the current slave address by starting a slave address set-

up process (see Section 6.2.6 on page 119). PEC is not supported for this transaction. Since this is a broadcast transaction,

all slave devices connected to the ACCESS.bus respond to it.

Write Internal Transaction

This transaction writes a byte of data to a register of a functional block of the PC8741x device. The functional block is se-

lected by the Logical Device Number for the ACCESS.bus (see Table 33 on page 123). The specific register is accessed

using the 8-bit offset address (from the base of the functional block). If PEC is supported, the master sends a PEC byte at

the end of the transaction.

If the selected Logical Device is not powered (the VDD supply is off), the PC8741x device generates a NACK bit at the end

of the Command byte, sets the OFFLDN bit in the ACBCST register (see Section 6.3.2 on page 127) and aborts the trans-

action.

Read Internal Transaction

This transaction reads a byte of data from a register of a functional block of the PC8741x device. The functional block is

selected by the Logical Device Number for the ACCESS.bus (see Table 33 on page 123). The specific register is accessed

using the 8-bit offset address (from the base of the functional block). This transaction is executed in two phases:

The master executes an ACCESS.bus write transaction, which conveys the Command (Read) and Offset Address

information to the PC8741x device. During this phase, the data is read from the speciﬁc register into the Read Buffer.

This phase has no Stop Condition.

Following a Restart condition, the master executes an ACCESS.bus read transaction. During this phase the data is

transferred from the Read Buffer to the master. At the end of this phase, the PC8741x device returns a PEC byte if

required by the master. The calculated PEC value is based on the bytes transferred during both phases.

If the selected Logical Device is not powered (the VDD supply is off), the PC8741x device generates a NACK bit at the end

of the Command byte, sets the OFFLDN bit in the ACBCST register (see Section 6.3.2 on page 127) and aborts the trans-

action.

General Call Address

Reset & Reload Slave Address

(00h)

(06h)

= Start condition

= ACK by slave

= Stop condition

Slave Address

Command

Offset Address

Data

PEC

(S.A, Write)

(OA7-OA0)

(Int, Write, LDN)

= Start condition

= ACK by slave

= Stop condition

Slave Address

Command

Offset Address

Data

PEC

(S.A, Write)

(OA7-OA0)

(Int, Read, LDN)

= Start condition

= Restart condition

= Stop condition

Slave Address

(S.A, Read)

= ACK by slave

A = ACK by master

= NACK by master

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