PC87413 datasheet(203/257 Pages) NSC

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9.0 System Wake-Up Control (SWC) (Continued)

Revision 1.2

203

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9.3.35

Watchdog Configuration Register (WDCFG)

This register contains the enable bits for the watchdog trigger sources. Reset all the bits before writing a new value to the

WDTO register. It is reset by hardware to 00h.

Power Well:VSB

Location:Bank 3, Offset 12h

Type:

R/W

Bit

76543210

Name

SW_WD

_TREN

Reserved

SER2_IRQ

_TREN

SER1_IRQ

_TREN

MS_IRQ

_TREN

KBD_IRQ

_TREN

Reset

00000000

Bit

Description

SW_WD_TREN (Software Watchdog Trigger Enable). Enables the event of the software writing a ‘1’ to the

SW_WD_TRG bit in the WDCTL register (see Section 9.3.33) to trigger the watchdog to start a new count.

0: Disable trigger (default)

1: Enable trigger by the SW_WD_TRG bit in the WDCTL register

6-4

Reserved.

SER2_IRQ_TREN (Serial Port 2 IRQ, Watchdog Trigger Enable). Enables an active IRQ from the Serial Port

2 to trigger the watchdog to start a new count.

0: Disable trigger (default)

1: Enable trigger by an active IRQ from the Serial Port 2

SER1_IRQ_TREN (Serial Port 1 IRQ, Watchdog Trigger Enable). Enables an active IRQ from the Serial Port

1 to trigger the watchdog to start a new count.

0: Disable trigger (default)

1: Enable trigger by an active IRQ from the Serial Port 1

MS_IRQ_TREN (Mouse IRQ, Watchdog Trigger Enable). Enables an active IRQ from the mouse interface

section of the KBC module to trigger the watchdog to start a new count.

0: Disable trigger (default)

1: Enable trigger by an active IRQ from the mouse interface section of the KBC module

KBD_IRQ_TREN (Keyboard IRQ, Watchdog Trigger Enable). Enables an active IRQ from the keyboard

interface section of the KBC module to trigger the watchdog to start a new count.

0: Disable trigger (default)

1: Enable trigger by an active IRQ from the keyboard interface section of the KBC module

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