RM0319 datasheet(243/368 Pages) STMICROELECTRONICS

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RM0319

Synchronous serial ports (SSP)

Doc ID 022640 Rev 3

243/368

transmit output disable bit (SOD). This can be used in some multislave environments where

masters might parallel broadcast.

To enable the operation of the SSP set the Synchronous Serial Port Enable (SSE) bit to 1.

Bit rate generation

Dividing down the PCLK derives the serial bit rate. The clock is first divided by an even

prescale value CPSDVSR from 2 to 254, which is programmed in SSPCPSR. The clock is

further divided by a value from 1 to 256, which is 1 + SCR, where SCR is the value

programmed in SSPCR0.

The frequency of the output signal bit clock SSPx_CLK is:

SSPxCLK

PCLK

CPSDVSR

SCR

()

⋅

---------------------------------------------------------------

For example, if PCLK is 3.6864 MHz, and CPSDVSR = 2, then SSPx_CLK has a frequency

range from 7.2 kHz to 1.8432 MHz.

18.5.5

Frame format

Each data frame is between 4 and 16 bits long depending on the size of data programmed,

and is transmitted starting with the MSB. There are three basic frame types that can be

selected:

●

Texas Instruments synchronous serial

●

Motorola SPI

●

National semiconductor microwire.

For all three formats, the serial clock (SSPx_CLK) is held inactive while the SSP is idle, and

transitions at the programmed frequency only during active transmission or reception of

data. The idle state of SSPx_CLK is utilized to provide a receive timeout indication that

occurs when the receive FIFO still contains data after a timeout period.

For Motorola SPI and National Semiconductor Microwire frame formats, the serial frame

(SSPx_SS) pin is active LOW, and is asserted (pulled down) during the entire transmission

of the frame.

For Texas Instruments synchronous serial frame format, the SSPx_SS pin is pulsed for one

serial clock period starting at its rising edge, prior to the transmission of each frame. For this

frame format, both the SSP and the off-chip slave device drive their output data on the rising

edge of SSPx_CLK, and latch data from the other device on the falling edge.

Unlike the full-duplex transmission of the other two frame formats, the National

Semiconductor Microwire format uses a special master-slave messaging technique, which

operates at half-duplex. In this mode, when a frame begins, an 8 bit control message is

transmitted to the off-chip slave. During this transmission no incoming data is received by

the SSP. After the message has been sent, the off-chip slave decodes it and, after waiting

one serial clock after the last bit of the 8 bit control message has been sent, responds with

the requested data. The returned data can be 4 to 16 bits in length, making the total frame

length anywhere from 13 to 25 bits.

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