RM0319 datasheet(242/368 Pages) STMICROELECTRONICS

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Synchronous serial ports (SSP)

RM0319

242/368

Doc ID 022640 Rev 3

The frequency selected for SSPCLK must accommodate the desired range of bit clock

rates. The ratio of minimum SSPCLK frequency to SSPCLKOUT maximum frequency in the

case of the slave mode is 12 and for the master mode it is two.

To generate a maximum bit rate of 1.8432 Mbps in the master mode, the frequency of

SSPCLK must be at least 3.6864 MHz. With an SSPCLK frequency of 3.6864 MHz, the

SSPCPSR register must be programmed with a value of two and the SCR[7:0] field in the

SSPCR0 register needs to be programmed as zero.

To work with a maximum bit rate of 1.8432 Mbps in the slave mode, the frequency of

SSPCLK must be at least 22.12 MHz. With an SSPCLK frequency of 22.12 MHz, the

SSPCPSR register can be programmed with a value of 12 and the SCR[7:0] field in the

SSPCR0 register can be programmed as zero. Similarly the ratio of SSPCLK maximum

frequency to SSPCLKOUT minimum frequency is 254 x 256.

The minimum frequency of SSPCLK is governed by the following equations, both of which

have to be satisfied:

FSSPCLK(min) => 2 x FSSPCLKOUT(max) [for master mode]

FSSPCLK(min) => 12 x FSSPCLKIN(max) [for slave mode]

The maximum frequency of SSPCLK is governed by the following equations, both of which

have to be satisfied:

FSSPCLK(max) <= 254 x 256 x FSSPCLKOUT(min) [for master mode]

FSSPCLK(max) <= 254 x 256 x FSSPCLKIN(min) [for slave mode]

18.5.3

Programming the SSPCR0 control register

The SSPCR0 register is used to:

●

Program the serial clock rate

●

Select one of the three protocols

●

Select the data word size (where applicable).

The Serial Clock Rate (SCR) value, in conjunction with the SSPCPSR clock prescale divisor

value (CPSDVSR), is used to derive the SSP transmit and receive bit rate from PCLK.

The frame format is programmed through the FRF bits and the data word size through the

DSS bits.

Bit phase and polarity, applicable to Motorola SPI format only, are programmed through the

SPH and SPO bits.

18.5.4

Programming the SSPCR1 control register

The SSPCR1 register is used to:

●

Select master or slave mode

●

Enable a loop back test feature

●

Enable the SSP peripheral.

To configure the SSP as a master, clear the SSPCR1 register master or slave selection bit

(MS) to 0, which is the default value on reset.

Setting the SSPCR1 register MS bit to 1 configures the SSP as a slave. When configured as

a slave, enabling or disabling of the transmit signal is provided through the slave mode

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