RM0319 datasheet(244/368 Pages) STMICROELECTRONICS

244 / 368 page

Synchronous serial ports (SSP)

RM0319

244/368

Doc ID 022640 Rev 3

18.6

Interrupts

There are five interrupts generated by the SSP. Four of these are individual, maskable,

active HIGH interrupts:

●

SSP receive FIFO service interrupt request.

●

SSP transmit FIFO service interrupt request.

●

SSP receive overrun interrupt request

●

SSP time out interrupt request.

The fifth is a combined single interrupt.

You can mask each of the four individual maskable interrupts by setting the appropriate bits

in the SSPIMSC register. Setting the appropriate mask bit HIGH enables the interrupt.

Provision of the individual outputs as well as a combined interrupt output, allows use of

either a global interrupt service routine, or modular device drivers to handle interrupts.

The transmit and receive dynamic dataflow interrupts have been separated from the status

interrupts, so that data can be read or written in response to just the FIFO trigger levels.

The status of the individual interrupt sources can be read from SSPRIS and SSPMIS

registers.

18.6.1

Receive interrupt

This interrupt is asserted when there is four or more valid entries in the receive FIFO.

18.6.2

Transmit interrupt

This interrupt is asserted when there are four or less valid entries in the transmit FIFO. The

transmitter interrupt is not qualified with the SSP enable signal, which allows operation in

one of two ways. Data can be written to the transmit FIFO prior to enabling the SSP and the

interrupts. Alternatively, the SSP and interrupts can be enabled so that data can be written

to the transmit FIFO by an interrupt service routine.

18.6.3

Receive overrun interrupt

This interrupt is asserted when the FIFO is already full and an additional data frame is

received, causing an overrun of the FIFO. Data is over-written in the receive shift register,

but not the FIFO.

18.6.4

Receive timeout interrupt

This interrupt is asserted when the receive FIFO is not empty and the SSP has remained

idle for a fixed 32 bit period. This mechanism ensures that the user is aware that data is still

present in the receive FIFO and requires servicing. This interrupt is deasserted if the receive

FIFO becomes empty by subsequent reads, or if new data is received. It can also be cleared

by writing to the RTIC bit in the SSPICR register.

18.6.5

Combined interrupt

This interrupt is an OR function of the individual masked sources. You can connect this

output to the system interrupt controller to provide another level of masking on an individual

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