RM0319 datasheet(230/368 Pages) STMICROELECTRONICS

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I2C bus ports (I2C)

RM0319

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Doc ID 022640 Rev 3

Otherwise, the FIFO will fill with data (overflow). To prevent this condition, the user must

correctly set the watermark level.”

Choosing the Receive Watermark Level

Similar to choosing the transmit watermark level described earlier, the receive watermark

level should be set to minimize the probability of overflow. It is a trade-off between the

number of DMA burst transactions required per block versus the probability of an overflow

occurring.

17.4

Operation modes

The I2C interface protocol is setup with a master and a slave. The master is responsible for

generating the clock and controlling the transfer of data. The slave is responsible for either

transmitting or receiving data to/from the master. The acknowledgement of data is sent by

the device that is receiving data, which can be either the master or the slave. The protocol

also allows multiple masters to reside on the I2C bus, which requires the masters to arbitrate

for ownership.

According to this specification, the I2C controller provided by the device supports three

distinct operation modes, specifically:

●

Slave mode (Section 17.4.1)

●

Master mode (Section 17.4.2)

●

Multimaster mode (Section 17.4.3)

17.4.1

Slave mode

This section provides information on the slave mode of operation.

Initial configuration

To use the I2C controller as a slave, you must perform the following steps:

Disable the I2C controller by writing a ‘b0 to the IC_ENABLE register.

Write to the IC_SAR register to set the slave address (only required if the slave address

to be programmed is other than 0x0055). This is the address to which the I2C controller

responds.

Write to the IC_CON register to specify whether 10 bit addressing is supported

(through IC_10BITADDR_SLAVE bit) and whether the I2C controller is in slave-only or

master-slave mode. The master-only mode is not valid in slave mode.

Enable the I2C controller setting the IC_ENABLE register.

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