RM0319 datasheet(228/368 Pages) STMICROELECTRONICS

228 / 368 page

I2C bus ports (I2C)

RM0319

228/368

Doc ID 022640 Rev 3

Transmitting and receiving protocol

All data is transmitted in byte format, with no limits on the number of bytes transferred per

data transfer. After the master sends the slave address and the data direction bit, or the

master transmits a byte of data to the slave, the slave-receiver must respond with the

acknowledge signal after every byte of data is received. When a slave-receiver does not

respond with an acknowledge pulse, the master aborts the transfer by issuing a STOP

condition. The slave shall leave the SDA line high so the master can abort the transfer.

If the master is receiving data, then the master-receiver responds to the slave-transmitter

with an acknowledge pulse after a byte of data has been received, except for the last byte.

This is the way the master-receiver notifies the slave-transmitter that this is the last byte.

The slave-transmitter relinquishes the SDA line after detecting the no acknowledge so that

the master-receiver can issue a STOP condition.

When the master does not want to relinquish the bus with a STOP condition, the master can

issue a repeated start condition. This is identical to a START condition except it occurs after

the acknowledge pulse. The master can then communicate with the same slave or with a

different slave.

START byte transfer protocol

The START byte transfer protocol is set up for systems that do not have an on-board

dedicated I2C hardware module. In this case, the systems can not be interrupted only by

requests from the I2C bus, but they must constantly monitor the bus (software polling).

When the I2C controller is addressed as a slave, it always samples the I2C bus at the

highest speed supported, so that it never requires START byte transfer. However, when the

I2C controller is a master, it supports the generation of START byte transfer at the beginning

of every transfer in case a slave device requires it.

As depicted in Figure 83 below, the start procedure is as follows:

●

Master generates a start condition (as explained above).

●

Master transmits the start byte (constant 8’b0000 0001).

●

Master transmits an acknowledge clock pulse.

●

No slave sets the acknowledge signal to 1‘b0.

●

Master generates a repeated START (Sr) condition.

Figure 83.

START byte procedure [from I2C-bus specification]

The START byte protocol consists of seven zeros being transmitted followed by a ‘b1 (the

start byte). This allows the system processor that is polling the bus to under-sample the

address phase until ‘b0 (low level on SDA) is detected. Once the system processor detects

a low level on SDA, it switches to a higher sampling rate to find the Sr condition of the

master (which is the one used for synchronization).

Dummy

Acknowledge HIGH

SCL

Start byte 00000001

ACK

SDA

RM0319 датащи(PDF) 228 Page - STMicroelectronics

RM0319 датащи(HTML) 228 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL