RM0319 datasheet(169/368 Pages) STMICROELECTRONICS

169 / 368 page

RM0319

Fast Ethernet ports (RMII0/RMII1/MII1)

Doc ID 022640 Rev 3

169/368

recognized to memory. The FIFO interface outputs all frames and asserts rx_w_err with

rx_w_eop if the frame is not addressed matched to indicate that the frame should be

discarded.

Whether a frame is copied depends on what is enabled in the network configuration register,

the state of the external match pin, the contents of the specific address and hash registers

and the frame's destination address. In this implementation of the MACB, the frame's source

address is not checked. Provided that bit 18 of the network configuration register is not set,

a frame will not be copied to memory if the MACB is transmitting in half duplex mode at the

time a destination address is received. If bit 18 of the network configuration register is set,

frames can be received while transmitting in half-duplex mode.

Ethernet frames are transmitted a byte at a time least significant bit first. The first six bytes

(48 bits) of an Ethernet frame make up the destination address. The first bit of the

destination address, the LSB of the first byte of the frame, is the group/individual bit: this is

One for multicast addresses and Zero for unicast. The All Ones address is the broadcast

address, and a special case of multicast.

This implementation of the MACB supports recognition of four specific addresses. Each

specific address requires two registers, specific address register bottom and specific

address register top. Specific address register bottom stores the first four bytes of the

destination address and specific address register top contains the last two bytes. The

addresses stored can be specific, group, local or universal.

The destination address of received frames is compared against the data stored in the

specific address registers once they have been activated. The addresses are deactivated at

reset or when their corresponding specific address register bottom is written. They are

activated when specific address register top is written. If a receive frame address matches

an active address, the frame is copied to memory.

The following example illustrates the use of the address match registers for a MAC address

of 21:43:65:87:A9:CB.

Table 57.

Address match register

Preamble

SFD

DA(Octet0 - LSB)

DA(Octet 1)

DA (Octet 2)

DA (Octet 3)

DA (Octet 4)

DA(Octet5 - MSB)

SA (LSB)

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