RM0319 datasheet(142/368 Pages) STMICROELECTRONICS

142 / 368 page

Fast Ethernet port (MII0)

RM0319

142/368

Doc ID 022640 Rev 3

12.3

Functional description

Figure 44 shows the system-level block diagram of MII0.

Figure 44.

MII0 system-level block diagram

12.3.1

AHB slave interface

The AHB Slave Interface block allows the host CPU to access all the DMA and MAC control

and status registers (CSRs).

32-/16- and 8-bit write/read transfers to CSRs are all supported by AHB Slave Interface, but

32-bit access to CSRs are recommended to avoid any software synchronization problems.

12.3.2

AHB master interface

The MII0 transfers data by DMA to system memory through the AHB master interface.

In particular, the AHB master interfaces with the DMA controller and converts the internal

DMA request cycles into AHB cycles. Both fixed burst length (SINGLE, INCR4, INCR8,

INCR16) and unspecified burst length (SINGLE, INCR) transfer types are supported.

Note:

The DMA controller should request an AHB Burst Read transfer only when it has the

capability of accepting the received burst data completely. Indeed, data read from AHB is

always pushed into the DMA without any delay.

The DMA controller should request an AHB Burst Write transfer only when it has the

sufficient data to transfer the burst completely. Indeed, the AHB interface assumes that it

always has data available to push into the AHB bus.

RxFIFO

(Mem)

TxFIFO

(Mem)

AHB

Master

Interface

AHB

Slave

Interface

DMA

TxFC RxFC

DMA

CSR

OMR

MAC

CSR

MAC-CORE

MAC-MTL

MAC-DMA

MAC-AHB

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