RM0319 datasheet(146/368 Pages) STMICROELECTRONICS

146 / 368 page

Fast Ethernet port (MII0)

RM0319

146/368

Doc ID 022640 Rev 3

Figure 46.

DMA descriptor format (Transmit Descriptor, 32 bit)

Table 44.

Transmit descriptor 0 (TDES0)

Bit

Name

Description

[31]

OWN

Own Bit. If set, indicates that the descriptor is owned by the DMA of MAC. If

cleared, the descriptor is owned by the host.

[30]

Interrupt on Completion. Setting this bit, the TI bit of the Status register (DMA

Register5) is set after the present frame has been transmitted.

[29]

Last Segment. If set, it indicates that the buffer contains the last segment of

the frame.

[28]

First Segment. If set, it indicates that the buffer contains the first segment of

the frame.

[27]

Disable CRC. Setting this bit, the MAC does not automatically add padding

to a framer shorter than 64 bytes.

[26]

Disable Padding. Setting this bit, the MAC does not automatically add

padding to a frame shorter than 64 bytes.

If cleared, the DMA automatically adds padding and CRC to a frame shorter

that 64 bytes and the CRC field is added despite the state if the DC bit

(TDES0[27]). Valid only if (TDES0[28]) is set.

[25]

TTSE

Reserved

[24]

Reserved

[23:22]

CIC

Checksum Insertion Control. These bits control the checksum calculation

and insertion. Bit encodings are as shown below.

2’b00: Checksum Insertion Disabled.

2’b01: Only IP header checksum calculation and insertion are enabled.

2’b10: IP Header checksum and payload checksum calculation and insertion

are enabled, but pseudo-header checksum is calculated in hardware.

2’b11: IP Header checksum and payload checksum calculation and insertion

are enabled, and pseudo-header checksum is calculated in hardware.

[21]

TER

Transmit End of Ring. If set, it indicates that the descriptor list reached its

final descriptor. The DMA returns to the base address of the list, creating a

descriptor ring structure.

TDES0

TDES1

TDES2

TDES3

Ctrl

[30:26]

Reserved

[25:24]

Ctrl

[23:20]

Reserved

[19:17]

Status [16:0]

Reserved

[31:29]

Buffer 2 Byte Count

[28:16]

Reserved

[15:13]

Buffer 1 Byte Count

[12:0]

Buffer 1 Address [31:0]

Buffer 2 Address [31:0] or Next Descriptor Address [31:0]

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