RM0319 datasheet(141/368 Pages) STMICROELECTRONICS

141 / 368 page

RM0319

Fast Ethernet port (MII0)

Doc ID 022640 Rev 3

141/368

Fast Ethernet port (MII0)

This chapter focuses on MII0 functionality and operation.

For technical details about the programmable registers related to the MII, refer to the MII

registers in the following companion document:

●

RM0321: SPEAr320S address map and registers

12.1

Overview

The MII0 controller is an Ethernet MAC 10/100 able to transmit and receive data over

Ethernet in compliance with the IEEE 802.3-2002 standard.

MII0 is configured to offer an AHB-interfaced native DMA (also referred as MAC-AHB) over

a MAC core. The MAC-AHB allows data transfer by DMA with system memory through the

AHB interface.

12.2

Main features

●

Supports the default Media Independent Interface (MII) defined in the IEEE 802.3

specifications.

●

Supports 10/100 Mbps data transfer rates with the PHY interfaces above.

●

Supports both half-duplex and full-duplex operation. In half-duplex operation,

CSMA/CD protocol is provided.

●

Programmable frame length to support both standard and Jumbo Ethernet frames with

size up to 16 Kbytes

●

A variety of flexible address filtering modes supported

●

A set of control and status registers (CSRs) to control MAC Core operation

●

Complete network statistics with RMON Counters (MMC, MAC Management Counters)

MAC-AHB main features

●

DMA implements dual-buffer (ring) or linked-list (chained) descriptor chaining.

●

A set of CSRs to control DMA operation

●

An AHB slave acting as programming interface to access all CSRs, for both DMA and

MAC Core subsystems

●

An AHB master for data transfer to system memory

●

It support both big-endian and little-endian

●

Power management module (PMT) with remote wake-up and magic packet frame

processing options

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