RM0319 datasheet(138/368 Pages) STMICROELECTRONICS

138 / 368 page

USB 2.0 Device ports (UDC)

RM0319

138/368

Doc ID 022640 Rev 3

11.4.6

Operation modes in DMA mode

Packet-per-buffer mode

In packet-per-buffer mode (alternate to buffer fill mode, Buffer fill mode (OUT) on page 138),

the DMA transfers packet by packet to various addresses as indicated by the descriptor,

implementing then a true scatter-gather mechanism.

A descriptor update can happen either at the end of each packet transfer or at the end of the

descriptor chain only. As a results, the application may be interrupted either after processing

each descriptor or at the end of a descriptor chain, respectively. In particular, setting to 1‘b1

the DU bit of the global CSRs Device control register, it enables descriptor updating and

application interrupt to the software at the end of each packet.

Buffer fill mode (OUT)

Enabling the buffer fill mode (setting the bit BF in the global CSRs Device control register,

the DMA transfers all packets to the large buffer whose address is indicated by the single

out data memory structure descriptor. This DMA mode of operation requires fewer memory

accesses than packet-per-buffer with descriptor update mode Packet-per-buffer mode on

page 138 above, increasing the throughput.

The DMA controller updates buffer status when a short packet is received, and

simultaneously sends an interrupt to the application.

Buffer fill mode (IN)

In case of in transactions, the DMA buffer fill mode can be entered by using the packet-per-

buffer mode with only one descriptor indicating:

●

The system memory starting address,

●

The number of bytes to be transferred to the USB Host (the tx bytes can be greater

than one packet),

●

The L bit set in the status quadlet.

The DMA controller updates buffer status after all data has been transferred to the TxFIFO.

The UDC-AHB subsystem then sends an interrupt to the application.

Threshold enable

The threshold enable feature is used for transferring packets in the out direction for DMA

operation only. There is no threshold enable for the in direction.

Note:

In this context, thresholding means emptying the out RxFIFO as soon as it receives a

certain number (the threshold value) of 32 bit words.

Thresholding is enabled by setting to 1‘b1 the THE bit in the global CSRs Device control

same device control register. As mentioned, the threshold value is the number of 32 bit

words (quadlets) that must be received by the RxFIFO before the DMA can start the

transfer.

When thresholding is disabled (bit THE set to 1‘b0), then the DMA waits for the complete

packet before starting the data transfer. In contrast, if thresholding is enabled, the transfer of

the packet to host memory starts before the validity of the packet is assessed. If the packet

is found to be corrupt at the end of the transfer, the descriptor is not updated and the next

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