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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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RM0319 датащи(PDF) 145 Page - STMicroelectronics |
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RM0319 датащи(HTML) 145 Page - STMicroelectronics |
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145 / 368 page  RM0319 Fast Ethernet port (MII0) Doc ID 022640 Rev 3 145/368 Figure 45. DMA descriptor list: ring structure (left) and chain structure (right). Note: The descriptor addresses must be aligned to the bus-width used (32/64/128 bit buses). Transmit descriptors As shown in Figure 46, there are four different transmit descriptors: ● Transmit Descriptor 0, TDES0 (Table 44): it contains the status of the transmitted frame and the descriptor ownership information along with control bits for controlling the descriptor structure and the frame being transferred. ● Transmit Descriptor 1, TDES1 (Table 45): it contains the data buffer sizes. ● Transmit Descriptor 2, TDES2 (Table 46): it contains the address pointer to the first data buffer in the descriptor. ● Transmit Descriptor 3, TDES3 (Table 47): it contains the address pointer to the second data buffer in the descriptor or the next descriptor (in case of chained structure). Buffer 1 Descriptor 0 Descriptor 1 Descriptor 2 Descriptor n Buffer 2 Buffer 1 Buffer 1 Buffer 1 Buffer 2 Buffer 2 Buffer 2 Buffer 1 Buffer 1 Buffer 1 Descriptor 0 Descriptor 1 Descriptor 2 Next Descriptor |
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