RM0319 datasheet(139/368 Pages) STMICROELECTRONICS

139 / 368 page

RM0319

USB 2.0 Device ports (UDC)

Doc ID 022640 Rev 3

139/368

clean packet overwrites the previous corrupted one. This conceals the USB error from the

application.

Burst split enable

When burst split is enabled, all AHB transfers (from the DMA to system memory and from

system memory to the TxFIFO) are splitted into bursts of a specified length.

The burst split is enabled by setting to 1‘b1 the BREN bit in the global CSRs’ Device control

same device control register. As mentioned, this value indicates the number of 32 bit

transfers that should happen in a single burst.

Note:

When thresholding and burst splitting are both enabled, the threshold length (THLEN)

should be either greater than multiples of burst length (BRLEN) or equal to BRLEN.

11.4.7

USB plug detect

The USB plug detect block (UPD) allows to detect when a USB Host is either connected or

disconnected to the USB 2.0 device. This is done through the VBUS pad which is driven

high when the USB Host is attached. In particular, a plug interrupt is raised by the UPD

block when the USB Host is attached/detached. This interrupt is putted in OR with the

output of the Interrupt Manager block and the output of he OR logic goes to the VIC block.

Two 32 bit RW registers are associated to the UPD block, namely the plug status register

and the plug pending register, whose bit assignments are given in Table 42 and Table 43,

respectively. These registers can be accessed at the base address 0xE1200000

As soon as the USB Host is connected to the device, the VBUS signal goes high enabling

the UPD internal counter, which generates an interrupt 10 ms after the connection. The

software routine handling the interrupt reads as 1‘b1 the intpend field of the plug pending

2.0 PHY reset is then released (phy_rst set to 1‘b0 in plug status register) and the USB 2.0

PHY is placed in normal mode (phy_mode set to 1‘b0 in plug status register).

In contrast, when the USB Host is detached, the VBUS signal goes low and after 10 ms an

interrupt is generated by the UPD block (intpend field set to 1‘b1 in plug pending register).

Then, the interrupt handler reads as 1‘b0 the state field of the plug status register, so the

reset is asserted (phy_rst set to 1‘b1 in Plug Status register) and the USB 2.0 PHY is placed

in non-driving state (phy_mode set to 1‘b1 in plug status register).

Table 42.

Plug status register bit assignments

Bit

Name

Reset value Description

[31:04]

Reserved

Read: undefined. Write: should be zero.

[03]

phy_mode

1’h1

USB PHY mode.

This bit allows to set the physical terminations of PHY,

according to encoding:

1‘b0 = Normal (UDC is allowed to drive the USB 2.0

PHY).

1‘b1 = Tri-state (the USB 2.0 PHY is in non-driving

mode).

RM0319 датащи(PDF) 139 Page - STMicroelectronics

RM0319 датащи(HTML) 139 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL