RM0319 datasheet(143/368 Pages) STMICROELECTRONICS

143 / 368 page

RM0319

Fast Ethernet port (MII0)

Doc ID 022640 Rev 3

143/368

12.3.3

DMA controller

The native DMA controller interfaces both with the host through the AHB interface and with

the MAC core (Section 12.2).

The DMA controller has Independent Transmit and Receive engines. The Transmit Engine

transfers data from system memory (through the AHB master interface) to MAC core, while

the Receive Engine transfers data from the MAC core to the system memory (through AHB

master interface).

Apart from DMA CSRs, the DMA controller communicates with the host using both

descriptor lists and data buffers.

The descriptor lists are used by the DMA Controller to efficiently move data from source to

destination with minimal host CPU involvement. The descriptor lists (detailed in

Section 12.3.7) reside in the host physical memory space, and they act as pointers to the

data buffer (each descriptor can point to two buffers maximum).

A data buffer consists of an entire frame or part of a frame, but cannot exceed a single

frame. Data buffers reside in the host physical memory space, and they are used by the

DMA Controller to write to (Receive Buffer) and read from (Transmit Buffer) frames which

have been received or have to be transmitted, respectively.

Note:

Only data are contained in data buffer, whereas buffer status is maintained in the relevant

descriptor.

12.3.4

Transmit and receive FIFO

The Transmit FIFO (TxFIFO) buffers data read from system memory by the DMA, before

transmission by the MAC core.

Similarly, the receive FIFO (RxFIFO) is intended to store the frames received from the

ethernet until they are transferred to system memory by the DMA.

These are asynchronous FIFOs, as they transfer data between the application clock domain

and the MAC line clock.

12.3.5

MAC management counters

The MMC (MAC Management Counters) module provides a mechanism compliant with the

standard RMON (Remote Networking Monitoring) specification. This standard defines a set

of statistics and functions that can be exchanged between RMON-compliant console

systems and network probes.

The counters in the MMC module can be viewed as an extension of the register address

space of the CSR module. The MMC module maintains a set of registers (see MAC_UNIV

MAC global registers) for gathering statistics on the received and transmitted frames. These

include a control register for controlling the behaviour of the registers, two 32-bit registers

containing interrupts generated (receive and transmit) and two 32-bit registers containing

mask for the interrupt register (receive and transmit).

The MMC registers are accessed using transactions, in the same way the CSR address

space is accessed.

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