MPC8569E datasheet(112/127 Pages) FREESCALE

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MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

SPI Interface

Freescale Semiconductor

112

2.18.2

PIC AC Timing Specifications

The following table provides the PIC input and output AC timing specifications.

2.19

SPI Interface

This section describes the SPI DC and AC electrical specifications of the MPC8569E.

2.19.1

SPI DC Electrical Characteristics

The following table provides the SPI DC electrical characteristics.

2.19.2

SPI AC Timing Specifications

The following table and provide the SPI input and output AC timing specifications.

Table 73. PIC Input AC Timing Specifications

For recommended operating conditions, see Table 3

Parameter

Symbol

Min

Max

Unit

Notes

PIC inputs—minimum pulse width

tPIWID

—

SYSCLK

Note:

1. PIC inputs and outputs are asynchronous to any visible clock. PIC outputs must be synchronized before use by any external

synchronous logic. PIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working in

edge-triggered mode.

Table 74. SPI DC Electrical Characteristics

For recommended operating conditions, see Table 3

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage

VIH

2.0

—

Input low voltage

VIL

—0.8

Input current (OVIN = 0 V or OVIN = OVDD)IIN

—

±40

μA2

Output high voltage (OVDD = min, IOH = –2 mA)

VOH

2.4

—

Output low voltage (OVDD = min, IOH = 2 mA)

VOL

—0.4

—

Note:

1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.

2. The symbol OVIN represents the input voltage of the supply. It is referenced in Table 3.

Table 75. SPI AC Timing Specifications

For recommended operating conditions, see Table 3

Parameter

Symbol1

Min

Max

Unit

Note

SPI outputs valid—Master mode (internal clock) delay

tNIKHOV

—6

SPI outputs hold—Master mode (internal clock) delay

tNIKHOX

0.5

—

SPI outputs valid—Slave mode (external clock) delay

tNEKHOV

—9

SPI outputs hold—Slave mode (external clock) delay

tNEKHOX

2—

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