MPC8569E datasheet(45/127 Pages) FREESCALE

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DDR2 and DDR3 SDRAM Controller

MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

2.3.2

Real Time Clock Timing

The real time clock timing (RTC) input is sampled by the core complex bus clock (CCB_clk). The output of the sampling latch

is then used as an input to the counters of the PIC and the time base unit of the e500; there is no need for jitter specification.

The minimum pulse width of the RTC signal must be greater than 2x the period of the CCB_clk. That is, minimum clock high

time is 2

× t

CCB_clk, and minimum clock low time is 2 × tCCB_clk. There is no minimum RTC frequency; RTC may be grounded

if not needed.

2.3.3

Gigabit Ethernet Reference Clock Timing

The following table provides the gigabit Ethernet reference clock (TX_CLK) AC timing specifications.

2.3.4

Other Input Clocks

A description of the overall clocking of this device is available in the MPC8569E PowerQUICC III Integrated Host Processor

Family Reference Manual in the form of a clock subsystem block diagram. For information about the input clock requirements

of other functional blocks such as SerDes, Ethernet Management, eSDHC, and Enhanced Local Bus see the specific interface

section.

2.4

DDR2 and DDR3 SDRAM Controller

This section describes the DC and AC electrical specifications for the DDR2 and DDR3 SDRAM controller interface of the

MPC8569E. Note that the required GVDD(typ) is 1.8 V for DDR2 SDRAM and GVDD(typ) is 1.5 V for DDR3 SDRAM.

Table 12. TX_CLK3,4 AC Timing Specifications

At recommended operating conditions with LVDD = 2.5 V ± 125 mV / 3.3 V ± 165 mV.

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

TX_CLK frequency

tG125

—125

—

MHz

—

TX_CLK cycle time

tG125

—8

—

TX_CLK rise and fall time

LVDD = 2.5 V

LVDD = 3.3 V

tG125R/tG125F

——

0.75

1.0

1, 5

TX_CLK duty cycle

GMII, TBI

1000Base-T for RGMII, RTBI

tG125H/tG125

—

%2, 5

TX_CLK jitter

—

± 150

2, 5

Notes:

1. Rise and fall times for TX_CLK are measured from 0.5 and 2.0 V for LVDD = 2.5 V, and from 0.6 and 2.7 V for LVDD =3.3 V.

2. TX_CLK is used to generate the GTX clock for the UEC transmitter with 2% degradation. The TX_CLK duty cycle can be

loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the UEC GTX_CLK. See

Section 2.6.3.7, “RGMII and RTBI AC Timing Specifications,” for duty cycle for 10Base-T and 100Base-T reference clock.

3. Gigabit transmit 125-MHz source. This signal must be generated externally with a crystal or oscillator, or is sometimes

provided by the PHY. TX_CLK is a 125-MHz input into the UCC Ethernet Controller and is used to generate all 125-MHz

related signals and clocks in the following modes: GMII, TBI, RTBI, RGMII.

4. For GMII and TBI modes, TX_CLK is provided to UCC1 through QE_PC[8:11,14,15] (CLK9-12,15,16) and to UCC2 through

QE_PC[2,3,6,7,15:17](CLK3,4,7,8,16:18). For RGMII and RTBI modes, TX_CLK is provided to UCC1 and UCC3 through

QE_PC11(CLK12) and to UCC2 and UCC4 through QE_PC16 (CLK17).

5. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is

guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing

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