MPC8569E datasheet(100/127 Pages) FREESCALE

100 / 127 page

MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

JTAG Controller

Freescale Semiconductor

100

The following figure provides the AC test load for TDO and the boundary-scan outputs of the device.

Figure 52. AC Test Load for the JTAG Interface

The following figure provides the JTAG clock input timing diagram.

Figure 53. JTAG Clock Input Timing Diagram

The following figure provides the TRST timing diagram.

Figure 54. TRST Timing Diagram

Input hold times

tJTDXKH

—

Output valid times:

Boundary-scan data

TDO

tJTKLDV

—

Output hold times

tJTKLDX

0—

Notes:

1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs

and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing

(JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to

the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D)

reaching the invalid state (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that in general, the clock

reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

3. All outputs are measured from the midpoint voltage of the falling edge of tTCLK to the midpoint of the signal in question. The

output timings are measured at the pins. All output timings assume a purely resistive 50-

Ω load. Time-of-flight delays must

be added for trace lengths, vias, and connectors in the system.

4. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is

guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing

Table 62. JTAG AC Timing Specifications (continued)

For recommended operating conditions, see Table 3

Parameter

Symbol1

Min

Max

Unit

Notes

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

JTAG

tJTKHKL

tJTGR

External Clock

tJTG

tJTGF

VM = Midpoint Voltage (OVDD/2)

TRST

VM = Midpoint Voltage (OVDD/2)

tTRST

MPC8569E датащи(PDF) 100 Page - Freescale Semiconductor, Inc

MPC8569E датащи(HTML) 100 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL