MPC8569E datasheet(38/127 Pages) FREESCALE

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MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Overall DC Electrical Characteristics

Freescale Semiconductor

Core power supply for SerDes transceiver

ScoreVDD

1.0 V ± 30 mV

1.1 V ± 33 mV

Pad power supply for SerDes transceiver

XVDD

1.0 V ± 30 mV

1.1 V ± 33 mV

DDR2 and DDR3 DRAM I/O voltage

GVDD

1.8 V ± 90 mV

1.5 V ± 75 mV

QUICC Engine block Ethernet interface I/O voltage

LVDD1

3.3 V ± 165 mV

2.5 V ± 125 mV

V—

QUICC Engine block Ethernet interface I/O voltage

LVDD2

3.3 V ± 165 mV

2.5 V ± 125 mV

V—

Debug, DMA, DUART, PIC, I2C, JTAG, power management, QUICC

Engine block, eSDHC, GPIO, clocking, SPI, I/O voltage select and

system control I/O voltage

OVDD

3.3 V ± 165 mV

—

Enhanced local bus I/O voltage

BVDD

3.3 V ± 165 mV

2.5 V ± 125 mV

1.8 V ± 90 mV

V—

Input voltage

DDR2 and DDR3 DRAM signals

MVIN

GND to GVDD

DDR2 DRAM reference

MVREF

GVDD/2 ± 2%

DDR3 DRAM reference

MVREF

GVDD/2 ± 1%

Ethernet signals

LVIN

GND to LVDDn

Enhanced local bus signals

BVIN

GND to BVDD

Debug, DMA, DUART, PIC, I2C, JTAG, power

management, QUICC Engine, eSDHC, GPIO,

clocking, SPI, I/O voltage select and system

control I/O voltage

OVIN

GND to OVDD

SerDes signals

XVIN

GND to XVDD

V—

Operating

Temperature

range

Commercial

TA,

TA = 0 (min) to

TJ = 105 (max)

oC—

Notes:

1. A nominal voltage of 1.1 V is recommended for CPU speeds of 1.33 GHz and QUICC Engine block speeds of 667 MHz.

2. This voltage is the input to the filter and not the voltage at the AVDD pin, which may be reduced from VDD by the filter.

3. Caution: (B,M,L,O,X)VIN must not exceed (B,G,L,O,X)VDD by more than 0.3 V. This limit may be exceeded for a maximum of

20 ms during power-on reset and power-down sequences.

4. The 1.8 V ± 90 mV range is for DDR2, and the 1.5 V ± 75 mV range is for DDR3.

Table 3. Recommended Operating Conditions (continued)

Characteristic

Symbol

Recommended

Value

Unit

Notes

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