MPC8569E datasheet(114/127 Pages) FREESCALE

114 / 127 page

MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

TDM/SI

Freescale Semiconductor

114

The following figure shows the SPI timing in master mode (internal clock).

Figure 66. SPI AC Timing in Master Mode (Internal Clock) Diagram

2.20

TDM/SI

This section describes the DC and AC electrical specifications for the time-division-multiplexed and serial interface of the

MPC8569E.

2.20.1

TDM/SI DC Electrical Characteristics

The following table provides the DC electrical characteristics for the MPC8569E TDM/SI.

2.20.2

TDM/SI AC Timing Specifications

The following table provides the TDM/SI input and output AC timing specifications.

NOTE: Rise/Fall Time on QE Input Pins

The rise / fall time on QE input pins should not exceed 5ns. This must be enforced

especially on clock signals. Rise time refers to signal transitions from 10% to 90% of Vcc;

fall time refers to transitions from 90% to 10% of Vcc.

Table 76. TDM/SI DC Electrical Characteristics

Characteristic

Symbol

Min

Max

Unit

Notes

Output high voltage (OVDD = min, IOH = –2 mA)

VOH

2.4

—

Output low voltage (OVDD = min, IOH = 2 mA)

VOL

—0.4

—

Input high voltage

VIH

2.0

OVDD +0.3

—

Input low voltage

VIL

–0.3

0.8

—

Input current (0 V

≤ V

IN ≤ OVDD)IIN

—±40

μA1

Note:

1. The symbol VIN, in this case, represents the OVIN referenced in Table 2 and Table 3.

SPICLK (output)

tNIIXKH

tNIKHOV

Input Signals:

SPIMISO

(See Note)

Output Signals:

SPIMOSI

(See Note)

tNIIVKH

tNIKHOX

Note: The clock edge is selectable on SPI.

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