MPC8569E datasheet(36/127 Pages) FREESCALE

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MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Overall DC Electrical Characteristics

Freescale Semiconductor

Electrical Characteristics

This section provides the AC and DC electrical specifications for the MPC8569E. This device is currently targeted to these

specifications, some of which are independent of the I/O cell, but are included for a more complete reference. These are not

purely I/O buffer design specifications.

2.1

Overall DC Electrical Characteristics

This section covers the DC ratings, conditions, and other characteristics.

2.1.1

Absolute Maximum Ratings

The following table provides the absolute maximum ratings.

26. These JTAG pins have weak internal pull-up P-FETs that are always enabled.

27. When operating in DDR2 mode, connect Dn_MDIC[0] to ground through an 18.2-

Ω (full-strength mode) or 36.4-Ω

(half-strength mode) precision 1% resistor and connect Dn_MDIC[1] to GVDD through an 18.2-Ω (full-strength mode) or

36.4-

Ω (half-strength mode) precision 1% resistor. When operating in DDR3 mode, connect Dn_MDIC[0] to ground through

a 20-

Ω (full-strength mode) or 40.2-Ω (half-strength mode) precision 1% resistor and connect Dn_MDIC[1] to GV

DD through

a 20-

Ω (full-strength mode) or 40.2-Ω (half-strength mode) precision 1% resistor. These pins are used for automatic

calibration of the DDR IOs.

28. Recommend a pull-up resistor (1 k

Ω) to be placed on this pin to OV

DD.

29. For systems which boot from local bus (GPCM)-controlled NOR flash or (FCM)-controlled NAND flash, a pull up on LGPL4

is required.

30. If unused, these pins must be connected to GND.

31. If unused, these pins must be left unconnected.

32. These pins may be connected to a temperature diode monitoring device such as the On Semiconductor, NCT1008™. If a

temperature diode monitoring device is not connected, these pins may be connected to test point or left as a no connect.

Table 2. Absolute Maximum Ratings1

Characteristic

Symbol

Range

Unit

Notes

Core supply voltage

VDD

–0.3 to 1.21

—

PLL supply voltage

AVDD_CORE

AVDD_DDR,

AVDD_LBIU,

AVDD_PLAT,

AVDD_QE,

AVDD_SRDS

–0.3 to 1.21

—

Core power supply for SerDes transceiver

ScoreVDD

–0.3 to 1.21

—

Pad power supply for SerDes transceiver

XVDD

–0.3 to 1.21

—

DDR2 and DDR3 DRAM I/O voltage

GVDD

–0.3 to 1.98

–0.3 to 1.65

QUICC Engine block Ethernet interface I/O voltage

LVDD1

–0.3 to 3.63

–0.3 to 2.75

V—

Table 1. MPC8569E Pinout Listing (continued)

Signal1

Package Pin Number

Pin Type

Power Supply

Note

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