MPC8569E datasheet(64/127 Pages) FREESCALE

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MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Ethernet Interface

Freescale Semiconductor

Duty cycle for Gigabit

tRGTH/tRGT

Rise time (20%–80%)

tRGTR

—

1.75

Fall time (20%–80%)

tRGTF

—

1.75

Notes:

1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII and

RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note also that the notation for rise

(R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is

skew (SK) followed by the clock that is being skewed (RGT).

2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns is

added to the associated clock signal. Many PHY vendors already incorporate the necessary delay inside their chip. If so,

additional PCB delay is probably not needed.

3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long

as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned

between.

5. The frequency of RX_CLK should not exceed the frequency of gigabit ethernet reference clock by more than 300 ppm.

6. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is

guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.

Table 35. RGMII and RTBI AC Timing Specifications (continued)

For recommended operating conditions, see Table 3

Parameter

Symbol1

Min

Typ

Max

Unit

Notes

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