MPC8569E datasheet(80/127 Pages) FREESCALE

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MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

High-Speed SerDes Interfaces (HSSI)

Freescale Semiconductor

may often differ from one component’s output to the other’s input. It may be different between the

receiver input and driver output circuits within the same component. It is also referred to as the DC

offset on some occasions.

To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a

common mode voltage of 2.25 V and outputs, TD and TD. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak

voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred to as the single-ended swing for each signal. Because

the differential signaling environment is fully symmetrical in this example, the transmitter output’s differential swing (VOD) has

the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500 mV and –500 mV.

In other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV.

The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.

2.9.2

SerDes Reference Clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding

SerDes lanes.The SerDes reference clock inputs are SD_REF_CLK and SD_REF_CLK for PCI Express, Serial RapidIO, and

SGMII interface, respectively.

The following sections describe the SerDes reference clock requirements and provide application information.

2.9.2.1

SerDes Spread Spectrum Clock Source Recommendations

SD_REF_CLK/SD_REF_CLK are designed to work with spread spectrum clock for PCI Express protocol only with the

spreading specification defined in Table 47. When using spread spectrum clocking for PCI Express, both ends of the link

partners should use the same reference clock. For best results, a source without significant unintended modulation must be used.

The spread spectrum clocking cannot be used if the same SerDes reference clock is shared with other non-spread spectrum

supported protocols. For example, if the spread spectrum clocking is desired on a SerDes reference clock for PCI Express and

the same reference clock is used for any other protocol such as SGMII/SRIO due to the SerDes lane usage mapping option,

spread spectrum clocking cannot be used at all.

2.9.2.2

SerDes Reference Clock Receiver Characteristics

The following figure shows a receiver reference diagram of the SerDes reference clocks.

Table 47. SerDes Spread Spectrum Clock Source Recommendations

At recommended operating conditions. See Table 3.

Parameter

Min

Max

Unit

Notes

Frequency modulation

kHz

—

Frequency spread

–0.5

Note:

1. Only down spreading is allowed.

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